User Dip Switches (Active-High) And I/O Header - Xilinx KCU1250 User Manual

User DIP Switches (Active-High) and I/O Header

The DIP switch SW3 (callout 26,
which connect to user I/O pins on the FPGA, as shown in
to set control pins or any other purpose you choose. The eight I/Os also map to a test
header J95 (callout 29,
can be connected to the onboard system controller as additional GPIO between the two
devices.
Install J7 to connect the user DIP switches to the system controller.
IMPORTANT:
Table 1-13: User DIP Switches
Pin Function
J19 User switch
J14 User switch
G19 User switch
F19 User switch
J18 User switch
H18 User switch
F18 User switch
F19 User switch
KCU1250 User Guide
UG1057 (v1.0) December 19, 2014
Figure 1-2) provides a set of eight active-High switches
Figure 1-2), providing external access for these pins. The I/O pins
FPGA(U1)
Direction IOSTANDARD
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
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Chapter 1: KCU1250 Board Features and Operation
Table 1-13. These pins can be used
DIP Switch
Schematic
Reference
Net Name
Designator
USER_SW1
USER_SW2
USER_SW3
USER_SW4
SW3
USER_SW5
USER_SW6
USER_SW7
USER_SW8
J95 Test
Device(U38)
Header
Pin
Pin
1 F12
3 E13
5 E11
7 E12
9 F13
11 F14
13 G15
15 F15
26
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