Spi External Programming Header - Xilinx AC701 User Manual

The configuration section of UG470, 7 Series FPGAs Configuration User Guide provides details
on using the Quad-SPI Flash memory.
Flash memory on the AC701 board. For more details, see the Micron N25Q256A13ESF40G
data sheet
X-Ref Target - Figure 1-5
VCC3V3
R20 R19
DNP 4.7kΩ 5%
FLASH_D3
R429
15Ω 1%
QSPI_IC_CS_B
R430
15Ω 1%
FLASH_D1

SPI External Programming Header

In addition to the QSPI device FPGA U1 connections shown in
interface is connected to an external programming header J7.
Table 1-6
Table 1-6: SPI J7 Connections to the FPGA
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
[Ref 4].
VCC3V3
C18
0.1µF 25V
X5R
R21
4.7kΩ 5%
GND
FLASH_D3_R
FLASH_D2_R
Figure 1-5: 256 Mb Quad-SPI Flash memory
shows the SPI J7 connections to FPGA U1.
Schematic Net
U1 FPGA Pin
Name
AE16 FPGA_PROG_B
N14 FLASH_D3
P14 FLASH_D2
J3.2 QSPI_CS_B
R14 FLASH_D0
R15 FLASH_D1
H13 FPGA_CCLK
NA GND
NA VCC3V3
www.xilinx.com
Figure 1-5 shows the connections of the Quad-SPI
VCC3V3
U7
N25Q256
R17
256 Mb Serial
DNP
Flash Memory
1 16
C
HOLD_B/DQ3
2 15
DQ0
VCC
3 14
NC7
NC0
4 13
NC6
NC1
5 12
NC5
NC2
6 11
NC4
NC3
7 10
VSS
SB
8 9
FLASH_D2_R
WB/VPP/DQ2
DQ1
GND
J7 Pin
1
2
3
4
5
6
7
8
9
Feature Descriptions
R18
4.7kΩ 5%
FPGA_CCLK
FLASH_D0_R FLASH_D0
R432
15Ω 1%
R431
15Ω 1%
FLASH_D2
UG952_c1_05_101812
Table 1-5, the FPGA U1 SPI
17