Xadc Header - Xilinx KC705 User Manual

Chapter 1: KC705 Evaluation Board Features
Table 1-32: Power Rail Specifications for UCD9248 PMBus controller at Address 53 (Cont'd)
Rail Rail Schematic
Number Name Rail Name
3 Rail #3 MGTAVCC
4 Rail #4 MGTAVTT
Notes:
1. The values defined in these columns are the voltage, current, and temperature thresholds that will cause the regulator to shut down
if the value is exceeded.
Table 1-33
UCD9248 PMBus controller at Address 54 (U89).
Table 1-33: Power Rail Specifications for UCD9248 PMBus controller at Address 54
Rail Rail Schematic
Number Name Rail Name
1 Rail #1 VCCAUX_IO
2 Rail #2 VCC_BRAM
3 Rail #3 MGTVCCAUX
Notes:
1. The values defined in these columns are the voltage, current, and temperature thresholds that will cause the regulator to shut down
if the value is exceeded.
For more information about the UCD9248PFC, PTD08A010W, PTD08A020W,
PTD08D021W, LMZ12002, TL1962ADC, and TPS51200DR power system components see
[Ref

XADC Header

[Figure
7 Series FPGAs provide an Analog Front End (XADC) block. The XADC block includes a
dual 12-bit, 1 MSPS Analog-to-Digital Convertor (ADC) and on-chip sensors.
See UG480, 7 Series FPGAs XADC Dual 12-Bit 1MSPS Analog-to-Digital Converter User Guide
for details on the capabilities of the analog front end.
XADC support features.
66
1 0.9 0.85
1.2 1.08 1.02
defines the voltage and current values for each power rail controlled by the
2 1.8 1.7
1 0.9 0.85
1.8 1.62 1.53
9].
1-2, callout 33]
www.xilinx.com
0 5 7 1
0 5 8 1
0 5 2 1
0 5 9 1
0 5 6 1
Figure 1-37
(1)
Shutdown Threshold
1.45 10.41 90
1.38 10.41 90
(1)
Shutdown Threshold
10.41 90
10.41 90
10.41 90
shows the KC705 board
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013