Quad-Spi Flash Memory - Xilinx ZC702 User Manual

Table 1-4: DDR3 Component Memory Connections to the XC7Z020 AP SoC (Cont'd)
XC7Z020 (U1) Pin
H7
P7
The ZC702 DDR3 4x 8-bit component memory interface adheres to the constraints guidelines
Note:
documented in the DDR3 Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions
v1.8 User Guide (UG586)
implementation. Other memory interface details are available in UG586 and the 7 Series FPGAs
Memory Resources User Guide (UG473)

Quad-SPI Flash Memory

[Figure 1-2, callout 3]
The Quad-SPI flash memory located at U41 provides 128 Mb of non-volatile storage that
can be used for configuration and data storage.
• Part number: N25Q128A11ESF40G (Micron/Numonyx)
• Supply voltage: 1.8V
• Data path width: 4 bits
• Data rate: Various depending on Single/Dual/Quad mode
The connections between the SPI flash memory and the XC7Z020 AP SoC are listed in
Table 1-5.
Table 1-5: Quad SPI Flash Memory Connections to the XC7Z020 AP SoC
XC7Z020 (U1)
Pin Name
PS_MIO6
PS_MIO5
PS_MIO4
PS_MIO3
PS_MIO2
PS_MIO1
Notes:
Each three-pin MIO select header has pin 1 wired to VCCMIO and pin 3 wired to GND.
The configuration and QSPI section of the Zynq-7000 All Programmable SoC Technical
Reference Manual (UG585)
ZC702 Board User Guide
UG850 (v1.3) June 4, 2014
Net Name
VTTVREF_PS
VTTVREF_PS
[Ref 10]. The ZC702 DDR3 memory interface is a 40Ω impedance
[Ref
Bank Pin Number
500 A4
500 A3
500 E4
500 F6
500 A2
500 A1
[Ref 9] provides details on using the Quad-SPI flash memory.
www.xilinx.com
Component Memory
Pin Number Pin Name
5].
Quad-SPI Flash Memory (U41) MIO Select
Schematic
Net Name
Pin Number
QSPI_CLK 16
QSPI_IO3 1
QSPI_IO2
9
QSPI_IO1 8
QSPI_IO0 15
QSPI_CS_B 7
Feature Descriptions
Reference
Designator
Header
Pin Name
C J26.2
DQ3_HOLD_B J25.2
WP_B J22.2
DQ1 J20.2
DQ0 J21.2
S_B NA
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