Quad-Spi Flash Memory - Xilinx ZC702 User Manual

Hide thumbs Also See for ZC702:
Table of Contents

Advertisement

Table 1-4: DDR3 Component Memory Connections to the XC7Z020 AP SoC (Cont'd)
XC7Z020 (U1) Pin
G4
L7
L6
M6
N4
N5
V3
R4
P3
R5
F3
P6
P5
M7
N7
H7
P7
Note:
The ZC702 DDR3 4x 8-bit component memory interface adheres to the constraints guidelines
documented in the DDR3 Design Guidelines section of 7 Series FPGAs Memory Interface Solutions
v1.8 User Guide (UG586). The ZC702 DDR3 memory interface is a 40Ω impedance implementation.
Other memory interface details are available in UG586 and 7 Series FPGAs Memory Resources
User Guide (UG473).

Quad-SPI Flash Memory

[Figure
1-2, callout 3]
The Quad-SPI flash memory located at U41 provides 128 Mb of non-volatile storage that
can be used for configuration and data storage.
Part number: N25Q128A11ESF40G (Micron/Numonyx)
Supply voltage: 1.8V
Data path width: 4 bits
Data rate: Various depending on Single/Dual/Quad mode
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
Net Name
PS_DDR3_A14
PS_DDR3_BA0
PS_DDR3_BA1
PS_DDR3_BA2
PS_DDR3_CLK_P
PS_DDR3_CLK_N
PS_DDR3_CKE
PS_DDR3_WE_B
PS_DDR3_CAS_B
PS_DDR3_RAS_B
PS_DDR3_RESET_B
PS_DDR3_CS_B
PS_DDR3_ODT
PS_VRN
PS_VRP
VTTVREF_PS
VTTVREF_PS
www.xilinx.com
Component Memory
Pin Number
Pin Name
N7
A14
J2
BA0
K8
BA1
J3
BA2
F7
G7
CK_B
G9
CKE
H3
WE_B
G3
CAS_B
F3
RAS_B
N2
RESET_B
H2
CS_B
G1
ODT
Feature Descriptions
Reference
Designator
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
CK
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
19

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents