Quad-Spi Flash Memory - Xilinx AC701 User Manual

Chapter 1: AC701 Evaluation Board Features
Table 1-4: DDR3 Memory Connections to the FPGA (Cont'd)
The AC701 board DDR3 memory interface adheres to the constraints guidelines
documented in the DDR3 Design Guidelines section of UG586, 7 Series FPGAs Memory
Interface Solutions User Guide. The AC701 board DDR3 memory interface is a 40Ω
impedance implementation. Other memory interface details are available in
UG473, 7 Series FPGAs Memory Resources User Guide

Quad-SPI Flash Memory

[Figure
The Quad-SPI Flash memory U7 provides 256 Mb of non-volatile storage that can be used
for configuration and data storage.
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Four data lines and the FPGA's CCLK pin are wired to the Quad-SPI Flash memory. The
connections between the SPI Flash memory and the FPGA are listed in
Table 1-5: Quad-SPI Flash Memory Connections to the FPGA
16
U1 FPGA Pin Net Name
P1 DDR3_RAS_B
P4 DDR3_CKE0
N4 DDR3_CKE1
L2 DDR3_CLK0_N
M2 DDR3_CLK0_P
N2 DDR3_CLK1_N
N3 DDR3_CLK1_P
1-2, callout 3]
Part number: N25Q256A13ESF40G (Micron)
Supply voltage: 3.3V
Datapath width: 4 bits
Data rate: Various depending on Single/Dual/Quad mode and CCLK rate
U1 FPGA Pin Net Name
R14 FLASH_D0
R15 FLASH_D1
P14 FLASH_D2
N14 FLASH_D3
H13 FPGA_CCLK
P18 QSPI_IC_CS_B
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J1 DDR3 Memory
Pin Number Pin Name
110 RAS_B
73 CKE0
74 CKE1
103 CK0_N
101 CK0_P
104 CK1_N
102 CK1_P
.
U7 Quad-SPI Flash Memory
Pin Number Pin Name
15 DQ0
8 DQ1
9 DQ2
1 DQ3
16 C
7 S_B
UG952 (v1.2) August 28, 2013
UG586 and
Table 1-5.
AC701 Evaluation Board