Quad-Spi Flash Memory - Xilinx ZC702 User Manual

Table 1-4: DDR3 Component Memory Connections to the XC7Z020 SoC (Cont'd)
XC7Z020 (U1) Pin
P3
R5
F3
P6
P5
M7
N7
H7
P7
The ZC702 DDR3 4x 8-bit component memory interface adheres to the constraints guidelines
Note:
documented in the DDR3 Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions
v1.8 User Guide (UG586)
implementation. Other memory interface details are available in UG586 and the 7 Series FPGAs
Memory Resources User Guide (UG473)
data sheet at the Micron website

Quad-SPI Flash Memory

[Figure 1-2, callout 3]
The Quad-SPI flash memory located at U41 provides 128 Mb of non-volatile storage that
can be used for configuration and data storage.
• Part number: N25Q128A11ESF40G (Micron)
• Supply voltage: 1.8V
• Datapath width: 4 bits
• Data rate: Various depending on Single/Dual/Quad mode
The connections between the SPI flash memory and the XC7Z020 SoC are listed in
Table 1-5.
Table 1-5: Quad SPI Flash Memory Connections to the XC7Z020 SoC
XC7Z020 (U1)
Pin Name
PS_MIO6
PS_MIO5
PS_MIO4
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Net Name
PS_DDR3_CAS_B
PS_DDR3_RAS_B
PS_DDR3_RESET_B
PS_DDR3_CS_B
PS_DDR3_ODT
PS_VRN
PS_VRP
VTTVREF_PS
VTTVREF_PS
[Ref 4]. The ZC702 DDR3 memory interface is a 40
[Ref
[Ref 14].
Bank Pin Number
500 A4
500 A3
500 E4
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Component Memory
Pin Number Pin Name
G3
F3
N2 RESET_B
H2
G1
5]. For more details, see the Micron MT41J256M8HX-15E
Quad-SPI Flash Memory (U41) MIO Select
Schematic
Net Name
Pin Number
QSPI_CLK 16
QSPI_IO3 1
QSPI_IO2
9
Feature Descriptions
Reference
Designator
CAS_B U66, U67, U68, U69
RAS_B U66, U67, U68, U69
U66, U67, U68, U69
CS_B U66, U67, U68, U69
ODT U66, U67, U68, U69
impedance
Ω
Header
Pin Name
C J26.2
DQ3_HOLD_B J25.2
WP_B J22.2
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