Pci Express Endpoint Connectivity - Xilinx VC709 User Manual

PCI Express Endpoint Connectivity

[Figure
The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a
Gen1 application, 5.0 GT/s for a Gen2 application, and 8.0 GT/s for a Gen3 application.
The PCIe transmit and receive signal datapaths have a characteristic impedance of
85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair. The 7 series FPGAs GTH
transceivers are used for multi-gigabit per second serial interfaces.
The XC7VX690T-2FFG1761CES FPGA (-2 speed grade) included with the VC709 board
supports up to Gen3 x8.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin AB8, and
the _N net is connected to pin AB7. The PCI Express clock circuit is shown in
X-Ref Target - Figure 1-13
PCIe lane width/size is selected through jumper J49
selection is 1-lane (J49 pins 1 and 2 jumpered).
X-Ref Target - Figure 1-14
Table 1-10
Table 1-10: PCIe Edge Connector Connections
Net Name FPGA (U1) Pin
PCIE_RX0_P
PCIE_RX0_N
PCIE_RX1_P
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
1-2, callout 11]
P1
PCI Express
Eight-Lane
Edge Connector
GND
REFCLK+
REFCLK-
GND
Figure 1-14: PCI Express Lane Size Select Jumper J49
lists the PCIe edge connector connections at P1.
PCIe Edge
Connector (P1)
Pin Name
Y4 B14 PETp0
Y3 B15 PETn0
AA6 B19 PETp1
www.xilinx.com
OE
A12
A13
PCIE_CLK_Q0_C_P
A14
PCIE_CLK_Q0_C_N
A15
GND
Figure 1-13: PCI Express Clock
J49
PCIE_PRSNT_X1
1 2
PCIE_PRSNT_X4 3 4
PCIE_PRSNT_X8
5 6
Function
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Feature Descriptions
C544
0.01μF 25V
X7R
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
C545
0.01μF 25V
X7R
UG887_c1_13_090612
(Figure 1-14). The default lane size
PCIE_PRSNT_B
UG887_c1_14_083112
FFG1761 Placement
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y22
Figure 1-13.
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