Pci Express Endpoint Connectivity - Xilinx VC707 User Manual

Evaluation board for the virtex-7 fpga

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Table Of Contents

Table of Contents

VC707 Evaluation Board Features

Chapter 1:

PCI Express Endpoint Connectivity

[Figure

The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5 gigatransfers per

second (GT/s) for a Gen1 application and 5.0 GT/s for a Gen2 application. The PCIe transmit and

receive signal datapaths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as

a 100Ω differential pair. The 7 series FPGAs GTX transceivers are used for multi-gigabit per second

serial interfaces.

The XC7VX485T-2FFG1761C FPGA (-2 speed grade) included with the VC707 board supports up

to Gen2 x8.

The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the

MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin AB8, and the

_N net is connected to pin AB7. The PCI Express clock circuit is shown in

X-Ref Target - Figure 1-14

PCIe lane width/size is selected through jumper J49

1-lane (J49 pins 1 and 2 jumpered).

X-Ref Target - Figure 1-15

Table 1-12

PCIe Edge Connector Connections GTX Quad 115

Table 1-12:

FPGA (U1)

Net Name

PCIE_RX0_P

PCIE_RX0_N

PCIE_RX1_P

AA6

PCIE_RX1_N

AA5

PCIE_RX2_P

AB4

PCIE_RX2_N

AB3

PCIE_RX3_P

AC6

Send Feedback

1-2, callout 13]

PCI Express

Eight-Lane

Edge connector

GND

REFCLK+

REFCLK-

GND

Figure 1-14: PCI Express Clock

PCIE_PRSNT_X1

PCIE_PRSNT_X4

PCIE_PRSNT_X8

Figure 1-15: PCI Express Lane Size Select Jumper J49

lists the PCIe edge connector connections at P1.

PCIe Edge Connector (P1)

Name

B14

PETp0