Pci Express Endpoint Connectivity - Xilinx VC707 User Manual

PCI Express Endpoint Connectivity

[Figure
The 8-lane PCI Express edge connector performs data transfers at the rate of
2.5 gigatransfers per second (GT/s) for a Gen1 application and 5.0 GT/s for a Gen2
application. The PCIe transmit and receive signal datapaths have a characteristic
impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair. The 7 series
FPGAs GTX transceivers are used for multi-gigabit per second serial interfaces.
The XC7VX485T-2FFG1761C FPGA (-2 speed grade) included with the VC707 board
supports up to Gen2 x8.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin AB8, and
the _N net is connected to pin AB7. The PCI Express clock circuit is shown in
X-Ref Target - Figure 1-14
PCIe lane width/size is selected through jumper J49
selection is 1-lane (J49 pins 1 and 2 jumpered).
X-Ref Target - Figure 1-15
Table 1-12
Table 1-12: PCIe Edge Connector Connections GTX Quad 115
FPGA (U1)
Net Name
Pin
PCIE_RX0_P Y4
PCIE_RX0_N Y3
PCIE_RX1_P AA6
PCIE_RX1_N AA5
PCIE_RX2_P AB4
PCIE_RX2_N AB3
PCIE_RX3_P AC6
VC707 Evaluation Board
UG885 (v1.4) May 12, 2014
1-2, callout 13]
P1
PCI Express
Eight-Lane
Edge connector
OE
GND
REFCLK+
REFCLK-
GND
Figure 1-14: PCI Express Clock
PCIE_PRSNT_X1
PCIE_PRSNT_X4
PCIE_PRSNT_X8
Figure 1-15: PCI Express Lane Size Select Jumper J49
lists the PCIe edge connector connections at P1.
PCIe Edge Connector (P1)
Pin Name
B14 PETp0 Integrated Endpoint block receive pair
B15 PETn0 Integrated Endpoint block receive pair
B19 PETp1 Integrated Endpoint block receive pair
B20 PETn1 Integrated Endpoint block receive pair
B23 PETp2 Integrated Endpoint block receive pair
B24 PETn2 Integrated Endpoint block receive pair
B27 PETp3 Integrated Endpoint block receive pair
www.xilinx.com
C544
0.01μF 25V
A12
X7R
A13
PCIE_CLK_Q0_C_P
A14
PCIE_CLK_Q0_C_N
A15
C545
0.01μF 25V
X7R
GND
(Figure
J49
PCIE_PRSNT_B
1 2
3 4
5 6
UG885_c1_15_020612
Function
Feature Descriptions
Figure 1-14.
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
UG885_c1_14_020612
1-15). The default lane size
FHG1761
Placement
GTXE2_CHANNEL_X1Y11
GTXE2_CHANNEL_X1Y11
GTXE2_CHANNEL_X1Y10
GTXE2_CHANNEL_X1Y10
GTXE2_CHANNEL_X1Y9
GTXE2_CHANNEL_X1Y9
GTXE2_CHANNEL_X1Y8
Send Feedback
35