Pci Express Endpoint Connectivity - Xilinx ML605 Hardware User's Manual

9. PCI Express Endpoint Connectivity

The 8-lane PCIe edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1
application and 5.0 GT/s for a Gen2 application. The Virtex FPGA GTX MGTs are used for
the multi-gigabit per second serial interfaces.
The ML605 board trace impedance on all PCIe lanes supports both Gen1 and Gen2
applications. The ML605 supports up to Gen1 x8 and Gen2 x4 as shipped with a -1 speed
grade for the LX240T device.
Figure 1-11
X-Ref Target - Figure 1-11
Note: PCIe edge connector signal nomenclature is
from perspective of the system/motherboard.
P1
REFCLK+,-
PERp,n[7:0]
PETp,n[7:0]
PCIe
8-Lane
Edge
Connector
PCIe lane width/size is selected via jumper J42 as shown in the figure below. The default
lane size selection is 1-lane (J42 pins 1 and 2 jumpered).
X-Ref Target - Figure 1-12
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
is a diagram of the PCIe MGT bank 114 and 115 clocking.
U14
PCIE_CLK_Q0_P/N
CLK/NCLK
ICS854104
PCIE_100M_MGT0_C_P/N
PCIE_100M_MGT0_P/N
U1
Bank 115
MGTREFCLK0 P/N
MGTTX
P/N[3:0]
Figure 1-11: PCIe MGT Banks 114 and 115 Clocking
PCIE_PRSNT_X1
PCIE_PRSNT_X4
PCIE_PRSNT_X8
Figure 1-12: PCIe Lane Size Select Jumper J42
www.xilinx.com
PCIE_100M_MGT1_P/N
Q1/NQ1
Q0/NQ0
MGTRX MGTTX
P/N[3:0] P/N[7:4]
PCIE_TX[7:0]_P/N
PCIE_RX[7:0]_P/N
J42
2
1
3 4
5 6
H-2X3
Detailed Description
U9
CLK/NCLK Q/NQ
ICS874001
PCIE_250M_MGT1_C_P/N
PCIE_250M_MGT1_P/N
U1
Bank 114
MGTREFCLK0 P/N
MGTRX
P/N[7:4]
UG534_11_100809
PCIE_PRSNT_B
UG534_12_111709
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