Pci Express Endpoint Connectivity - Xilinx VC709 User Manual

Chapter 1: VC709 Evaluation Board Features
Table 1-9: GTH Quad Connection Assignments (Cont'd)
For more information on the GTH transceivers see 7 Series FPGAs GTX/GTH Transceivers
User Guide (

PCI Express Endpoint Connectivity

[Figure
The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a
Gen1 application, 5.0 GT/s for a Gen2 application, and 8.0 GT/s for a Gen3 application.
The PCIe transmit and receive signal datapaths have a characteristic impedance of
85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair. The 7 series FPGAs GTH
transceivers are used for multi-gigabit per second serial interfaces.
The XC7VX690T-2FFG1761C FPGA (-2 speed grade) included with the VC709 board
supports up to Gen3 x8.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin AB8, and
the _N net is connected to pin AB7. The PCI Express clock circuit is shown in
34
Transceiver Bank
MGT_BANK_118
MGT_BANK_119
UG476 )
[Ref 5].
1-2, callout 11]
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Channel/Clock
GTHE2_CHANNEL_X1Y29
GTHE2_CHANNEL_X1Y28
MGTREFCLK0
MGTREFCLK1
GTHE2_CHANNEL_X1Y35
GTHE2_CHANNEL_X1Y34
GTHE2_CHANNEL_X1Y33
GTHE2_CHANNEL_X1Y32
MGTREFCLK0
MGTREFCLK1
GTHE2_CHANNEL_X1Y39
GTHE2_CHANNEL_X1Y38
GTHE2_CHANNEL_X1Y37
GTHE2_CHANNEL_X1Y36
MGTREFCLK0
MGTREFCLK1
Connections
FMC2 HPC DP8
FMC2 HPC DP9
NC
NC
FMC1 HPC DP7
FMC1 HPC DP6
FMC1 HPC DP5
FMC1 HPC DP4
FMC1 HPC GBT_CLK1
FMC2 HPC GBT_CLK0
FMC1 HPC DP3
FMC1 HPC DP2
FMC1 HPC DP1
FMC1 HPC DP0
NC
NC
Figure 1-14.
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014