Control Registers; Dmac Status Register; Dmac Configuration Register - Epson Arm S1C31 Series Technical Manual

6 DMA CONTROLLER (DMAC)

6.8 Control Registers

DMAC Status Register

Register name Bit
DMACSTAT 31–24 –
23–21 –
20–16 CHNLS[4:0]
15–8 –
7–4 STATE[3:0]
3–1 –
0
Bits 31–21 Reserved
Bits 20–16 CHNLS[4:0]
These bits show the number of DMAC channels implemented in this IC.
Number of channels implemented = CHNLS + 1
Bits 15–8 Reserved
Bits 7–4 STATE[3:0]
These bits indicates the DMA transfer status.
DMACSTAT.STATE[3:0] bits
Bits 3–1 Reserved
Bit 0 MSTENSTAT
This bit indicates the DMA controller status.
1 (R): DMA controller is operating.
0 (R): DMA controller is idle.

DMAC Configuration Register

Register name Bit
DMACCFG 31–24 –
23–16 –
15–8 –
7–1 –
0
Bits 31–1 Reserved
Bit 0 MSTEN
This bit enables the DMA controller.
1 (W): Enable
0 (W): Disable
6-10
Bit name Initial
0x00
0x0
*
0x00
0x0
0x0
MSTENSTAT 0
Table 6.8.1 DMA Transfer Status
0xf–0xbf Reserved
0xa Peripheral scatter-gather transfer is in progress.
0x9 Transfer has completed.
0x8 Transfer has been suspended.
0x7 Control data is being written.
0x6 Standby for transfer request to be cleared.
0x5 Transfer data is being written.
0x4 Transfer data is being read.
0x3 Transfer destination end pointer is being read.
0x2 Transfer source end pointer is being read.
0x1 Control data is being read.
0x0 Idle
Bit name Initial
0x00
0x00
0x00
0x00
MSTEN –
Seiko Epson Corporation
Reset R/W
– R –
– R
H0 R * Number of channels implemented - 1
– R –
H0 R
– R
H0 R
DMA transfer status
Reset R/W
– R –
– R
– R –
– R
– W
S1C31D41 TECHNICAL MANUAL
Remarks
Remarks
(Rev. 1.1)