Functional Description; Data Bus Structure; Microprocessor; Mc68Xx040 Cache - Motorola MVME162P2 Series Installation And Use Manual

Functional Description

Functional Description

Data Bus Structure

4

Microprocessor

MC68 xx 040 Cache
4-6
This section contains a functional description of the major blocks on the
MVME162P2.
The local bus on the MVME162P2 is a 32-bit synchronous bus that is
based on the MC68040 bus, and which supports burst transfers and
snooping. The various local bus master and slave devices use the local bus
to communicate. The local bus is arbitrated by priority type; the priority of
the local bus masters from highest to lowest is: 82596CA LAN, 53C710
SCSI, VMEbus, and MPU. As a general rule, any master can access any
slave; not all combinations pass the common sense test, however. Refer to
the MVME1X2P2 VME Embedded Controller Programmer's Reference
Guide and to the user's guide for each device to determine its port size, data
bus connection, and any restrictions that apply when accessing the device.
MVME162P2 models may be ordered with an MC68040 or MC68LC040
microprocessor.
The MC68040 has on-chip instruction and data caches and a floating-point
processor. (A floating-point coprocessor is the major difference between
the MC68040 and MC68LC040.) Refer to the MC68040 user's manual for
more information.
The MVME162P2 local bus masters (VMEchip2, processor, 53C710
SCSI controller, and 82596CA Ethernet controller) have programmable
control of the snoop/caching mode. The IP DMA local bus master's snoop
control function is governed by the settings of switch S5 segments 1 and 2
(refer to IP DMA Snoop Control (S5 Pins 1/2) on page
determines the value of the snoop control signal for all IP DMA transfers.
This includes the IP DMA which executes when the DMA control registers
are updated while the IP DMA is operating in command chaining mode.
Computer Group Literature Center Web Site
1-18). S5