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Programming Model
14.4.2
UART 1 Baud Control Register
The UART 1 baud control (UBAUD1) register controls the operation of the baud rate generator, the
integer prescaler, and the UCLK signal. The bit position assignments for this register are shown in the
following register display. The settings for this register are described in Table 14-5.
UBAUD1
BIT 15
14
TYPE
0
0
RESET
Table 14-5. UART 1 Baud Control Register Description
Name
Reserved
Reserved
Bits 15–14
UCLKDIR
UCLK Direction—This bit controls the direction
Bit 13
of the UCLK signal. When this bit is low, the sig-
nal is an input, and when it is high, it is an output.
However, the SELx bit in the Port E registers
must be 0. See Section 10.4.6, "Port E Regis-
ters," on page 10-21 for more information.
Reserved
Reserved
Bit 12
BAUD SRC
Baud Source—This bit controls the clock source
Bit 11
to the baud rate generator.
DIVIDE
Divide—These bits control the clock frequency
Bits 10–8
produced by the baud rate generator.
Reserved
Reserved
Bits 7–6
PRESCALER
Prescaler—These bits control the division value
Bits 5–0
of the baud generator prescaler. The division
value is determined by the following formula:
Prescaler division value =
65 (decimal) – PRESCALER
14-12
UART 1 Baud Control Register
13
12
11
10
UCL
BAU
KDI
D
R
SRC
rw
rw
rw
0
0
0
0
Description
MC68VZ328 User's Manual
9
8
7
6
5
DIVIDE
rw
rw
rw
0
0
0
0
1
0x003F
These bits are reserved and should be set to
0.
0 = UCLK is an input.
1 = UCLK is an output.
This bit is reserved and should be set to 0.
0 = Baud rate generator source is from
system clock.
1 = Baud rate generator source is from
UCLK pin (UCLKDIR must be set to 0).
000 = Divide by 1.
001 = Divide by 2.
010 = Divide by 4.
011 = Divide by 8.
100 = Divide by 16.
101 = Divide by 32.
110 = Divide by 64.
111 = Divide by 128.
These bits are reserved and should be set to
0.
See description.
0x(FF)FFF902
4
3
2
1
BIT 0
PRESCALER
rw
rw
rw
rw
rw
1
1
1
1
1
Setting
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