Lcd Controller Timing; Figure 19-13 Lcd Controller Timing Diagram (Normal Mode) - Motorola MC68VZ328 User Manual

Table 19-14. LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)
Number
9 RASx pulse width
10 CASx pulse width (BC[1:0] = 00,01,10,11 in FPM)
11 CASx precharge time
12 RASx negated to CASx negated
13 Data-in hold after CASx negated
14 OE negated after CASx negated
Note:
N is the number of words in one DMA transfer.
T is the system clock period.
RASx stands for RAS0 and RAS1. CASx stands for CAS0 and CAS1.
MSW is bit 5 and BC[1:0] comprises bits 13–12 in the DRAMC register. When the table identifies these bits, the
sequence of their listed values corresponds to the sequence of timing data provided.
19.3.13

LCD Controller Timing

Figure 19-13 shows the LCD controller timing diagram for normal mode, and Figure 19-14 on page 19-18
displays the timing diagram for self-refresh mode. The signal values and units of measure for both figures
are found in Table 19-15 on page 19-18. Detailed information about the operation of individual signals can
be found in Chapter 8, "LCD Controller," and Chapter 7, "DRAM Controller."
LFLM
LLP
LD[7:0]
LCLK
Figure 19-13. LCD Controller Timing Diagram (Normal Mode)
Timing Parameters (Continued)
Characteristic
3
Electrical Characteristics
AC Electrical Characteristics
(3.0 ± 0.3) V
Minimum Maximum
(2N + 1)T
28,58,88,118
26
-28
0
0
1
2
4
Unit
— ns
— ns
— ns
— ns
— ns
2 ns
19-17