Port M Data Register; Table 10-52 Port M Data Register Description - Motorola MC68VZ328 User Manual

Programming Model
10.4.11.2

Port M Data Register

The settings for the PMDATA register bit positions are shown in Table 10-52.
PMDATA
BIT 7
TYPE
RESET
Name
Reserved Reserved
Bits 7–6
Dx Data—These bits reflect the
Bits 5–0 status of the I/O signal in an
8-bit system.
Port M is multiplexed with the SDRAM controller signals. These pins can be programmed as GPIO when
the SDRAM I/O signals are not in use.
These bits control or report the data on the pins while the associated SELx bits are high. While the DIRx
bits are high (output), the Dx bits control the pins. While the DIRx bits are low (input), the Dx bits report
the signal driving the pins. The Dx bits can be written at any time. Bits that are configured as inputs will
accept the data, but the data written to each cannot be accessed until the corresponding pin is configured as
an output. The actual value on the pin is reported when these bits are read, regardless of whether they are
configured as input or output.
10-38
Port M Data Register
6 5
D5
rw
0 0 1
*Actual bit value depends on external circuits connected to pin.
Table 10-52. Port M Data Register Description
Description
These bits are reserved and should be set to 0.
0 = Drives the output signal low when DIRx is set to 1 or the
1 = Drives the output signal high when DIRx is set to 1 or the
MC68VZ328 User's Manual
4 3
D4 D3
rw rw
0 0
0x20*
Setting
external signal is low when DIRx is set to 0
external signal is high when DIRx is set to 0
0x(FF)FFF449
2 1 BIT 0
D2 D1 D0
rw rw rw
0 0 0