Dram Control Register; Table 7-7 Dram Control Register Description - Motorola MC68VZ328 User Manual

Programming Model
7.3.2

DRAM Control Register

The DRAM control (DRAMC) register is used to control the operation of the DRAM controller. The bit
position and values are shown in the following register display. The details about the register settings are
described in Table 7-7.
DRAMC
BIT 15 14
EN RM
TYPE rw rw
0 0
RESET
Name
EN Master DRAM Controller Enable—This bit
Bit 15 enables and disables the DRAM controller.
RM Refresh Mode—This bit sets the refresh mode.
Bit 14
BC1–0 Page Access Clock Cycle (Fast Page
Bit 13–12 Mode)—These bits determine the number of
additional clocks for the second and subsequent
accesses within a Fast Page Mode read cycle
after the first data word.
CLK Clock—This bit selects the clock that is provided
Bit 11 to the refresh timer.
EDO Extended Data Out—This bit selects the page
Bit 10 access mode for LCD DMA DRAM accesses.
This bit should only be set if the DRAM supports
EDO RAM transfers. When the EDO bit is set,
BC0 and BC1 do not affect the number of clocks
for LCD DMA DRAM accesses. EDO RAM mode
is the fastest LCD DMA transfer mode.
PGSZ Page Size—This field determines the page size
Bits 9–8 in the word for Fast Page Mode mode access.
Reserved Reserved
Bits 7–6
MSW Slow Multiplexing—Setting this bit adds a sys-
Bit 5 tem clock for DRAM address multiplexing, which
allows for a heavily loaded A/DMA bus. Setting
this bit causes an additional wait state for all core
accesses and the first LCD DMA word access.
7-14
DRAM Control Register
13 12 11 10 9
BC1–0 CLK EDO
rw rw rw rw rw
0 0 0 0 0
Table 7-7. DRAM Control Register Description
Description
1
MC68VZ328 User's Manual
8 7 6 5
PGSZ MSW
rw rw
0 0 0 0
0x0000
0 = Disable the DRAM controller.
1 = Enable the DRAM controller.
0 = CAS-before-RAS refresh mode.
1 = Self-refresh mode.
00 = 1 additional clock (2 clocks/transfer).
01 = 2 additional clocks (3 clocks/transfer).
10 = 3 additional clocks (4 clocks/transfer).
11 = 4 additional clocks (5 clocks/transfer).
0 = CLK32 (Period A) is selected.
1 = System clock (Period B) is selected.
0 = Fast Page Mode mode is selected.
1 = EDO enables 1 clock for each LCD DMA data
word transfer after the first word transfer.
Bits BC1–0 are ignored.
00 = 256
01 = 512
10 = 1,024
11 = 2,048
These bits are reserved and should be set to 0.
0 = Normal address multiplexing.
1 = Slower address multiplexing.
0x(FF)FFFC02
4 3 2 1
LSP SLW LPR RST
rw rw rw rw
0 0 0 1
Setting
BIT 0
DWE
rw
0