Lcd Polarity Configuration Register; Lacd Rate Control Register; Table 8-11 Lcd Polarity Configuration Register Description - Motorola MC68VZ328 User Manual

Programming Model
8.3.10

LCD Polarity Configuration Register

The LCD polarity configuration (LPOLCF) register controls the polarity of the interface signal that goes to
the LCD panel. The bit assignments for the register are shown in the following register display. The
settings for the bits in the register are listed in Table 8-11.
LPOLCF
BIT 7
TYPE
0
RESET
Table 8-11. LCD Polarity Configuration Register Description
Name
Reserved Reserved
Bits 7–4
LCKPOL LCD Shift Clock Polarity—This bit controls the polarity of the
Bit 3 active edge of the LCD shift clock.
FLMPOL Frame Marker Polarity—This bit controls the polarity of the
Bit 2 frame marker.
LPPOL Line Pulse Polarity—This bit controls the polarity of the line
Bit 1 pulse.
PIXPOL
Bit 0 Pixel Polarity—This bit controls the polarity of the pixels.
8.3.11

LACD Rate Control Register

The LCD alternate crystal direction rate control (LACDRC) register is used to control the alternate rates of
the liquid crystal direction. The bit assignments for the register are shown in the following register display.
The settings for the bits in the register are listed in Table 8-12 on page 8-17.
8-16
LCD Polarity Configuration Register
6 5
0 0
Description
MC68VZ328 User's Manual
4 3 2
LCKPOL FLMPOL
rw rw
0 0 0
0x00
These bits are reserved and should
be set to 0.
0 = Active negative edge of LCLK.
1 = Active positive edge of LCLK.
0 = Frame marker is active high.
1 = Frame marker is active low.
0 = Line pulse is active high.
1 = Line pulse is active low.
0 = Pixel polarity is active high.
1 = Pixel polarity is active low.
0x(FF)FFFA21
1 BIT 0
LPPOL PIXPOL
rw rw
0 0
Setting