Figure 19-4 Chip-Select Flash Write Cycle Timing Diagram; Table 19-6 Chip-Select Flash Write Cycle Timing Parameters - Motorola MC68VZ328 User Manual

A[31:0]
CSx
UWE/LWE
OE
D[15:0]
DTACK
Figure 19-4. Chip-Select Flash Write Cycle Timing Diagram
Table 19-6. Chip-Select Flash Write Cycle Timing Parameters
Number
1 Address valid to CSx asserted
(bit ECDS = 0, bit ECDS = 1)
2 CSx asserted to UWE/LWE asserted
3 CSx asserted to data-out valid
4 External DTACK input setup from CSx asserted
5 CSx pulse width
(bit ECDS = 0, bit ECDS = 1)
6 UWE/LWE negated before CSx is negated
7 External DTACK input hold after CSx is negated
8 Data-out hold after CSx is negated
9 CSx negated to data-out in Hi-Z
Note:
n is the number of wait states in the current memory access cycle.
T is the system clock period.
The external DTACK input requirement is eliminated when CSx is programmed to use the internal DTACK.
CSx stands for CSA0, CSA1, CSB0, CSB1, CSC0, CSC1, CSD0, or CSD1.
A value in parentheses is used when early detection is turned on.
1
2
3
4
Characteristic
Electrical Characteristics
AC Electrical Characteristics
5
6
9
8
7
(3.0 ± 0.3) V
Minimum
20, 20 - T/2
20
—
—
60 + nT,
(60 + T/2) + nT
10
0
8
—
Unit
Maximum
— ns
40 ns
30 ns
20 + nT ns
— ns
20 ns
— ns
— ns
18 ns
19-7