Motorola MC68VZ328 User Manual page 363

PCDATA register, 10-12
PDDATA register, 10-17
PEDATA register, 10-22
PFDATA register, 10-25
PGDATA register, 10-29
PJDATA register, 10-32
PKDATA register, 10-35
PMDATA register, 10-38
E
Early ASB delay processing for static memory early
detection bit, see EASP bit
Early ASB delay value field, see EASDLY[1:0] field
Early cycle detection for dynamic memory bit, see
ECDD bit
Early cycle detection for static memory bit, see ECDS
bit
Early cycle detection type bit, see ECDT bit
EASDLY[1:0] field, 6-19
EASP bit, 6-19
ECDD bit, 6-18
ECDS bit, 6-19
ECDT bit, 6-19
Edge enable field, see IQEGx field
EDO bit, 7-14
Electrical characteristics
AC, 19-2
DC maximum and minimum values, 19-2
maximum ratings, 19-1
EMIQ bit
IPR register, 9-16
ISR register, 9-12
EMIQ signal pin, 2-7
EMUCS register, 6-16
Emulation chip-select register, see EMUCS register
Emulation chip-select wait state bit, see EWSO bit
Emulation memory mapping, see ICE module
Emulator interrupt pending bit, see EMIQ bit
Emulator interrupt status bit, see EMIQ bit
EN bit
CSA register, 6-9
CSB register, 6-11
CSC register, 6-13
CSD register, 6-15
DRAMC register, 7-14
PWMC1 register, 15-5
ENABLE bit, 13-15
Enable bit, see EN bit, PWMC1 register
End write early bit, see EWE bit
ET1 bit, 9-8
ET2 bit, 9-9
ET3 bit, 9-9
ET6 bit, 9-9
EUPEN bit, 6-17
EWE bit, 6-20
EWSO bit, 6-17
Exception vector
assignments, 9-3 to 9-4
definition, 9-3
Exchange bit, see XCH bit
Execution b-record format, see bootstrap mode
EXTAL pin, description, 2-4
Extended data out, see EDO bit
External clock/crystal, see EXTAL pin
External INT0 interrupt bit, see INT0 bit
External INT1 interrupt bit, see INT1 bit
External INT2 interrupt bit, see INT2 bit
External INT3 interrupt bit, see INT3 bit
Extra UPSIZ bit enable bit, see EUPEN bit
F
Features of MC68VZ328, 1-2 to 1-4
FIFO available bit, see FIFOAV bit
FIFO empty (FIFO status) bit, see FIFO EMPTY bit
FIFO EMPTY bit
UTX1 register, 14-14
UTX2 register, 14-24
FIFO full (FIFO status) bit, see FIFO FULL bit
FIFO FULL bit
URX1 register, 14-13
URX2 register, 14-23
FIFO half (FIFO status) bit, see FIFO HALF bit
FIFO HALF bit
URX1 register, 14-13
URX2 register, 14-23
UTX1 register, 14-15
UTX2 register, 14-25
FIFO level marker interrupt register, see HMARK
register
FIFO overrun (character status) bit, see OVRUN bit
FIFOAV bit, 15-5
FLASH bit
CSA register, 6-8
CSC register, 6-12
CSD register, 6-15
Flash memory support bit, see FLASH bit
FLMPOL bit, 8-16
FLX68000, see CPU
Force parity error bit, see FORCE PERR bit
FORCE PERR bit
UMISC1 register, 14-16
UMISC2 register, 14-26
FPGA address comparator, see ICE module
Frame error (character status) bit, see FRAME ERROR
bit
FRAME ERROR bit
URX1 register, 14-14
URX2 register, 14-24
Index Index-v