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PGDATA
BIT 7
TYPE
RESET
Name
Description
Reserved
Reserved
Bits 7–6
Dx
Data—These bits reflect the
Bits 5–0
status of the I/O signal in an
8-bit system.
Port G is multiplexed with address line A0 and several dedicated I/O functions. These pins can be
programmed as GPIO when the address bus and the dedicated I/O signals are not in use.
All of the bits control or report the data on the pins while the associated SELx bits are high. While the
DIRx bits are high (output), the Dx bits control the pins. While the DIRx bits are low (input), the Dx bits
report the signal driving the pins. The Dx bits can be written at any time. Bits that are configured as inputs
will accept the data, but the data written to each cannot be accessed until the corresponding pin is
configured as an output. The actual value on the pin is reported when these bits are read, regardless of
whether they are configured as input or output. See Table 10-36 on page 10-28 for information about
setting the bits in the PGDIR register.
10.4.8.3
Port G Dedicated I/O Functions
The six PGDATA lines are multiplexed with the dedicated I/O signals whose assignments are shown in
Table 10-38.
Table 10-38. Port G Dedicated I/O Function Assignments
Bit
0
1
2
3
4
5
6
7
Port G Data Register
6
5
D5
rw
0
0
1
*Actual bit value depends on external circuits connected to pin.
Table 10-37. Port G Data Register Description
These bits are reserved and should be set to 0.
0 = Drives the output signal low when DIRx is set to 1 or the external
signal is low when DIRx is set to 0
1 = Drives the output signal high when DIRx is set to 1 or the external
signal is high when DIRx is set to 0
GPIO Function
I/O Ports
4
3
D4
D3
rw
rw
1
1
0x3F*
Setting
Dedicated I/O Function
Data bit 0
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Programming Model
0x(FF)FFF431
2
1
BIT 0
D2
D1
D0
rw
rw
rw
1
1
BUSW/DTACK
A0
EMUIRQ
HIZ/P/D
EMUCS
EMUBRK
1
10-29
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