Dram Write Cycle 16-Bit Access (Cpu Bus Master); Figure 19-7 Dram Write Cycle 16-Bit Access (Cpu Bus Master) Timing Diagram - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
Table 19-8. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Parameters (Continued)
Number
12 CASx asserted before column address
invalid
13 RASx negated after CASx is negated
14 RASx precharge time (SLW= 0,1)
Note: RASx stands for RAS0 and RAS1. CASx stands for CAS0 and CAS1.
Note: MSW is bit 5, SLW is bit 3, and BC[1:0] comprises bits 13–12 in the DRAMC register. When the table
identifies these bits, the sequence of their listed values corresponds to the sequence of timing data provided.
19.3.7

DRAM Write Cycle 16-Bit Access (CPU Bus Master)

Figure 19-7 shows the DRAM write cycle timing diagram for 16-bit access (CPU bus master). The signal
values and units of measure for this figure are found in Table 19-9 on page 19-11. Detailed information
about the operation of individual signals can be found in Chapter 7, "DRAM Controller," and Chapter 6,
"Chip-Select Logic."
MD[12:0]
RASx
CASx
DWE
OE
D[15:0]
Figure 19-7. DRAM Write Cycle 16-Bit Access (CPU Bus Master) Timing Diagram
19-10
Characteristic
Row
4
1
6
3
2
9
MC68VZ328 User's Manual
(3.0 ± 0.3) V
Minimum
50
28
58,118
Column
12
5
8 13
7
11
10
Unit
Maximum
— ns
— ns
— ns
Row
14