Table 6-10 Chip-Select Register D Description - Motorola MC68VZ328 User Manual

Programming Model
CSD
BIT
14
15
RO SOP ROP
TYPE rw rw
0 0
RESET
Name
RO Read-Only—This bit sets the chip-select to
Bit 15 read-only. Otherwise, read and write
accesses are allowed. A write to a read-only
area will generate a bus error if the BETEN bit
of the SCR is set. See Section 5.2.1, "System
Control Register," on page 5-2 for more infor-
mation.
SOP Supervisor-Use-Only Protected Memory
Bit 14 Block—This bit sets the protected memory
block to supervisor-only; otherwise, both
supervisor and user accesses are allowed.
Attempts to access the supervisor-only area
result in a bus error if the BETEN bit of the
SCR is set. See Section 5.2.1, "System Con-
trol Register," on page 5-2 for more informa-
tion.
ROP Read-Only for Protected Memory
Bit 13 Block—This bit sets the protected memory
block to read-only. Otherwise, read and write
accesses are allowed. If you write to a
read-only area, you will get a bus error.
UPSIZ Unprotected Memory Block Size—This field
Bits 12-11 determines the unprotected memory range of
the chip-select.
COMB Combining—This bit controls combining
Bit 10 RAS0 and RAS1 memory space to generate
RAS0. When this bit is set to 1, RAS1 can be
used as a general-purpose I/O signal.
DRAM DRAM Selection—This bit is used to enable
Bit 9 RAS and CAS signals. Configuring the CSC
register as a non-DRAM memory type
requires clearing the DRAM bit of the CSD
register.
Note: The DRAM bit overrides the flash bit.
6-14
Chip-Select Register D
13 12 11 10
UPSIZ COMB
rw rw rw
0 0 0 0
Table 6-10. Chip-Select Register D Description
Description
MC68VZ328 User's Manual
9 8 7
DRAM FLASH BSW
rw rw rw
1 0 0
0x0200
0 = Read/write.
1 = Read-only.
0 = Supervisor/user.
1 = Supervisor-only.
0 = Read/write.
1 = Read-only.
00 = 32K.
01 = 64K.
10 = 128K.
11 = 256K.
0 = RAS0 to RAS0 memory space.
1 = RAS0 covers both RAS0 and RAS1 memory
space B.
0 = Select CSC[1:0] and CSD[1:0].
1 = Select CAS and RAS.
0x(FF)FFF116
6 5 4 3 2
WS3–1 SIZ
rw rw rw rw rw rw
0 0 0 0 0
Setting
BIT
1
0
EN
w
0 0