Spi 1 Slave Fifo Advanced By Ss Rising Edge; Figure 19-32 Spi 1 Slave Fifo Advanced By Ss Rising Edge Timing Diagram - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
19.3.31

SPI 1 Slave FIFO Advanced by SS Rising Edge

Figure 19-32 shows the timing diagram for the SPI 1 slave FIFO advanced by SS rising edge. The signal
values and units of measure for Figure 19-27 through Figure 19-32 are found in Table 19-17. Detailed
information about the operation of individual signals can be found in Chapter 13, "Serial Peripheral
Interface 1 and 2."
SS
(Input)
SCLK,
MOSI, MISO
Figure 19-32. SPI 1 Slave FIFO Advanced by SS Rising Edge Timing Diagram
Table 19-17. Timing Parameters for Figure 19-27 Through Figure 19-32
Number
1 Clock edge to TxD data ready
2 RxD data ready to clock edge
3 Clock edge to RxD data hold time
4 DATA_READY to SS output low
5 SS output low to first SCLK edge
6 Last SCLK edge to SS output high
7 SS output high to DATA_READY low
8 SS output pulse width
9 SS input low to first SCLK edge
10 SS input pulse width
11 Pause between data word
Note:
T = SPI clock period
WAIT = Number of sysclk or 32.768 KHz clocks per sample period control register
19-34
9
11
Characteristic
MC68VZ328 User's Manual
10
(3.0 ± 0.3) V
Minimum
—
0.25T
0.25T
—
2T
T
T
2T + WAIT
T
0
0
Unit
Maximum
0.25T ns
— ns
— ns
2T ns
— ns
— ns
— ns
— ns
— ns
— ns
— ns