Table of Contents
Advertisement
Programming Model
10.4.5.7
Port D Interrupt Request Enable Register
The interrupt enable bits (IQEN[3:0]) determine which INT[3:0] will generate an interrupt to the interrupt
controller module. The settings for the bit positions of PDIRQEN are shown in Table 10-23.
PDIRQEN
BIT 7
TYPE
RESET
Table 10-23. Port D Interrupt Request Enable Register Description
Name
Reserved
Reserved
Bits 7–4
IQENx
Interrupt Enable—These bits select the INT[3:0]
Bits 3–0
pins that are presented to the interrupt controller.
10.4.5.8
Port D Keyboard Enable Register
All the selected signals are active low in reference to the external pins, and those that are asserted will
generate a keyboard interrupt to the interrupt controller. When a KBENx bit is selected, the DIRx bits need
to be configured as an input. The SELx, POLx, IQENx, and IQEGx bits have no effect on the functionality
of KBENx. Deasserting the interrupt source is the only way to clear a keyboard interrupt. The settings for
the bit positions of PDKBEN are shown in Table 10-24.
PDKBEN
BIT 7
KBEN7
TYPE
RESET
Table 10-24. Port D Keyboard Enable Register Description
Name
KBENx
Keyboard Enable—These bits select the INT[3:0]
Bits 7–0
pins that are presented to the interrupt controller.
10.4.5.9
Port D Interrupt Request Edge Register
The polarity of the rising or falling edge is selected by the POLx bits. It should be noted that the edge-level
interrupt for INT[3:0] cannot be used for system wake up. The level-sensitive interrupt should be used. The
settings for the bit positions of PDIRQEG are shown in Table 10-25 on page 10-21.
10-20
Port D Interrupt Request Enable Register
6
5
0
0
0
Description
Port D Keyboard Enable Register
6
5
KBEN6
KBEN5
rw
rw
rw
0
0
0
Description
MC68VZ328 User's Manual
4
3
2
IQEN3
IQEN2
rw
rw
0
0
0
0x00
These bits are reserved and should be set
to 0.
0 = Interrupt disabled.
1 = Interrupt enabled.
4
3
2
KBEN4
KBEN3
KBEN2
rw
rw
rw
0
0
0
0x00
0 = The keyboard interrupt is disabled.
1 = The keyboard interrupt is enabled.
0x(FF)FFF41D
1
BIT 0
IQEN1
IQEN0
rw
rw
0
0
Setting
0x(FF)FFF41E
1
BIT 0
KBEN1
KBEN0
rw
rw
0
0
Setting
Advertisement
Table of Contents
