Chip-Select Timing Trim; Dram Read Cycle 16-Bit Access (Cpu Bus Master); Figure 19-5 Chip-Select Timing Trim Timing Diagram; Table 19-7 Chip-Select Timing Trim Timing Parameters - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
19.3.5

Chip-Select Timing Trim

Figure 19-5 shows the timing diagram for the chip-select timing trim. The signal values and units of
measure for this figure are found in Table 19-7. For detailed information about the individual signals, see
Chapter 6, "Chip-Select Logic."
CLKO
CSx
CSx
UWE/LWE
UWE/LWE
Figure 19-5. Chip-Select Timing Trim Timing Diagram
Table 19-7. Chip-Select Timing Trim Timing Parameters
Number
1 CLKO high to CSx asserted (bit ECDS = 0)
2 CLKO low to CSx asserted (bit ECDS = 1)
3 UWE/LWE negated before CSx is negated (bit WPEXT = 0)
4 UWE/LWE negated before CSx is negated (bit WPEXT = 1)
19.3.6

DRAM Read Cycle 16-Bit Access (CPU Bus Master)

Figure 19-6 on page 19-9 shows the DRAM read cycle timing diagram for 16-bit access (CPU bus master).
The signal values and units of measure for this figure are found in Table 19-8 on page 19-9. Detailed
information about the operation of individual signals can be found in Chapter 7, "DRAM Controller," and
Chapter 6, "Chip-Select Logic."
19-8
S0 S2 S4
1
2
Characteristic
MC68VZ328 User's Manual
WS S6 S0
4
(3.0 ± 0.3) V
Minimum Maximum
—
—
10
40
3
Unit
10 ns
10 ns
20 ns
50 ns