Spi 1 And Spi 2 Generic Timing; Spi 1 Master Using Data_Ready Edge Trigger; Figure 19-27 Spi 1 And Spi 2 Generic Timing Diagram; Figure 19-28 Spi 1 Master Using Data_Ready Edge Trigger Timing Diagram - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
19.3.26

SPI 1 and SPI 2 Generic Timing

Figure 19-27 shows the timing diagram for SPI 1 and SPI 2. The signal values and units of measure for
Figure 19-27 through Figure 19-32 are found in Table 19-17 on page 19-34. Detailed information about
the operation of individual signals can be found in Chapter 13, "Serial Peripheral Interface 1 and 2."
SPICLK
(POL=1, PHA=1)
SPICLK
(POL=1, PHA=0)
SPICLK
(POL=0, PHA=1)
SPICLK
(POL=0, PHA=0)
TxD/MOSI
RxD/MISO
Figure 19-27. SPI 1 and SPI 2 Generic Timing Diagram
19.3.27

SPI 1 Master Using DATA_READY Edge Trigger

Figure 19-28 shows the timing diagram for the SPI 1 master using the DATA_READY edge trigger. The
signal values and units of measure for Figure 19-27 through Figure 19-32 are found in Table 19-17 on
page 19-34. Detailed information about the operation of individual signals can be found in Chapter 13,
"Serial Peripheral Interface 1 and 2."
SS
(Output)
DATA_READY
(Input)
SCLK,
MOSI, MISO
Figure 19-28. SPI 1 Master Using DATA_READY Edge Trigger Timing Diagram
19-32
1
B n B n–1 B n–2
2
B n B n–1 B n–2
4
5
7
MC68VZ328 User's Manual
B n–3
3
B n–3
8
6
B 1 B 0
B 1 B 0