Table 19-13 Lcd Dram Dma Cycle 16-Bit Edo Ram Mode Access (Lcd Bus Master) - Motorola MC68VZ328 User Manual

Table 19-13. LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)
Number
1 Row address valid to RASx asserted
2 DWE negated before row address valid
3 OE asserted before RASx asserted
4 RASx asserted before row address invalid
(MSW = 0,1)
5 Column address valid to CASx asserted
(MSW = 0,1)
6 RASx asserted to CASx asserted (MSW = 0,1)
7 CASx asserted to data-in valid
8 CASx asserted before column address invalid
9 RASX pulse width
10 CASx pulse width
11 CASx precharge time
12 RASx negated to CASx negated
13 Data-in hold after CASx negated
14 OE negated after CASx negated
Note:
N is the number of words in one DMA transfer.
T is the system clock period.
RASx stands for RAS0 and RAS1. CASx stands for CAS0 and CAS1.
MSW is bit 5 in the DRAMC register. When this bit is set to 0, the first timing number applies; when it is set to 1, the
second timing number applies.
Timing Parameters
Characteristic
Electrical Characteristics
AC Electrical Characteristics
(3.0 ± 0.3) V
Minimum Maximum
45 —
0 —
0 —
12,27 —
10,25 —
28,58 —
— 20
20 —
(2N + 1)T —
28 —
26 —
-28 —
30 —
28 32
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
19-15