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Function Group
Power
Ground
Regulator output
Clocks/PCIO
System control
Address bus/PFIO
Lower data bus/PAIO
Upper data bus
Bus control/PCIO/PEIO/
PKIO
Interrupt controller/PMIO
LCD controller/PCIO
UART1/PEIO, UART2/PJIO
Timer/PBIO
Pulse-width modulator/PBIO
Master SPI/PEIO, config-
urable SPI/PJIO/PKIO
Chip-select,
EDO RAM/PBIO, PMIO
SDRAM/PMIO
Emulator pins
No connect pins
Table 2-1. Signal Function Groups
Signals
V
DD
V
SS
LV
DD
XTAL, EXTAL, CLKO/PF2
RESET
PF[3:6]/A[23:20], A[19:14], A0/PG1,
MA[15:0]/A[16:1]
PA[7:0]/D[7:0]
D[15:8]
BUSW/DTACK/PG0, OE, LWE/LB, UWE/UB,
PE3/DWE/UCLK, PK2/LDS, PK3/UDS, PK1/RW
INT0/PD0, INT1/PD1, INT2/PD2, INT3/PD3,
IRQ1/PD4, IRQ2/PD5, IRQ3/PD6, IRQ6/PD7,
IRQ5/PF1
LACD/PC7, LCLK/PC6, LLP/PC5, LFLM/PC4,
LD[7:4]/PK[7:4], LD[3:0]/PC[3:0], LCON-
TRAST/PF0
PE4/RXD1, PE5/TXD1, PE6/RTS1, PE7/CTS1,
PJ4/RXD2, PJ5/TXD2, PJ6/RTS2, PJ7/CTS2
TOUT/TIN/PB6
PWMO1/PB7 (PM5/DATA_READY/PWMO2)
SPITXD/PE0, SPIRXD/PE1, SPICLK2/PE2,
PJ0/MOSI, PJ1/MISO, PJ2/SPICLK1, PJ3/SS,
PK0/DATA_READY/PWMO2
CSA[1:0]/PF7, CSB[1:0]/PB[1:0]/SDWE,
CSC[1:0]/PB[3:2]/RAS[1:0],
CSD[1:0]/PB[5:4]/CAS[1:0], PM5/DMOE
PM0/SDCLK, PM1/SDCE, PM2/DQMH,
PM3/DQML, PM4/SDA10, (SDWE, SDCAS[1:0],
SDRAS[1:0] )—multiplexed with chip-select sig-
nals
EMUIRQ/PG2, EMUBRK/PG5, HIZ/P/D/PG3,
EMUCS/PG4
NC
Signal Descriptions
Signals Grouped by Function
Number of Pins
TQFP
PBGA
9
5
16
28
5
1
3
3
1
1
24
24
8
8
8
8
8
8
9
9
13
13
8
8
1
1
1
1
8
8
9
9
5
5
4
4
4
0
2-3
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