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System Clock
(SYSCLK)
32 kHz Clock
External Reset
(Hardware Reset)
Internal Reset
Internal Reset
Pulse
Ports A, C, D, E,
F, G, J, & K
Ports B & M
As shown in Figure 10-1, resets for Ports A, C–G, J, and K are triggered by the assertion of the internal
reset signal. The internal reset signal is synchronized with the first falling edge of the 32 kHz clock after
the external reset has been asserted. The resets for Ports B and M are triggered by the negation of the
internal reset pulse signal. The sequence of events (as shown in Figure 10-1) leading to the assertion of the
internal reset pulse signal are as follows:
1. The external reset signal is negated.
2. The first falling edge of 32 kHz occurs.
3. After 16 cycles of SYSCLK, the internal reset pulse, whose width is 1 SYSCLK cycle, is
generated.
Port B and Port M are designed to maintain or hold their previous states during the Reset Assertion Time
Length to support the "data retention during reset" feature of the DRAM controller. Holding the previous
states of Port B and Port M allows multiplexed DRAM control signals to remain active during the system
Reset Assertion Time Length. This feature allows the DRAM controller to maintain the refresh cycles for
DRAM during unpredictable reset time lengths, thereby preserving DRAM data after reset negation. More
details appear in Chapter 7, "DRAM Controller."
10.2.2
Power-up Reset
The power-up reset sequence of events is the same as for a warm reset, except that the I/O states of Port B
and Port M are unknown during the Reset Assertion Time Length. Because Port B and Port M do not reset
until the negation of the internal reset pulse signal, they do not have a previous state on a power-up reset.
While preliminary testing indicates that, on power-up reset, Ports B and M are configured as inputs with
internal resistors enabled, this cannot be guaranteed. For any external device that may be sensitive to the
brief unknown states of Port B or Port M on power-up resets, it is recommended that the device be
connected to other available ports whose state can be ascertained.
External Reset Time Length
Figure 10-1. I/O Port Warm Reset Timing
I/O Ports
Status of I/O Ports During Reset
16 SYSCLK Cycles
Default State
Reset Assertion Time Length
Default State
10-3
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