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14.4.3
UART 1 Receiver Register
The UART 1 receiver (URX1) register indicates the status of the receiver FIFO and character data. The
FIFO status bits reflect the current status of the FIFO. At initial power up, these bits contain random data.
Before enabling the receiver interrupts, the UEN and RXEN bits in the USTCNT register should be set.
Reading the UART 1 receiver register initializes the FIFO status bits. The receiver interrupts can then be
enabled. However, the character status bits are only valid when read with the character bits in a 16-bit read
access. The bit position assignments for this register are shown in the following register display. The
settings for this register are described in Table 14-6.
URX1
BIT
14
15
FIFO
FIFO
FULL
HALF
TYPE
r
r
0
0
RESET
Name
FIFO
FIFO Full (FIFO Status)—This read-only bit indicates that the
FULL
receiver FIFO is full and may generate an overrun. This bit gen-
Bit 15
erates a maskable interrupt.
FIFO
FIFO Half (FIFO Status)—This read-only bit indicates that the
HALF
receiver FIFO has four or fewer slots remaining in the FIFO.
Bit 14
This bit generates a maskable interrupt.
DATA
Data Ready (FIFO Status)—This read-only bit indicates that at
READY
least 1 byte is present in the receive FIFO. The character bits
Bit 13
are valid only while this bit is set. This bit generates a maskable
interrupt.
OLD
Old Data (FIFO Status)—This read-only bit indicates that data
DATA
in the FIFO is older than 30 bit times. It is useful in situations
Bit 12
where the FIFO FULL or FIFO HALF interrupts are used. If
there is data in the FIFO, but the amount is below the FIFO
HALF interrupt threshold, a maskable interrupt can be gener-
ated to alert the software that unread data is present. This bit
clears when the character bits are read.
OVRUN
FIFO Overrun (Character Status)—This read-only bit indi-
Bit 11
cates that the receiver overwrote data in the FIFO. The charac-
ter with this bit set is valid, but at least one previous character
was lost. In normal circumstances, this bit should never be set.
It indicates the software is not keeping up with the incoming
data rate. This bit is updated and valid for each received char-
acter.
Universal Asynchronous Receiver/Transmitter 1 and 2
UART 1 Receiver Register
13
12
11
OV
DATA
OLD
FRAME
RU
READY
DATA
ERROR
N
r
r
r
0
0
0
Table 14-6. UART 1 Receiver Register Description
Description
10
9
8
PARITY
BREAK
ERROR
r
r
r
0
0
0
0x0000
0 = Receiver FIFO is not full
1 = Receiver FIFO is full
0 = Receiver FIFO has more than
1 = Receiver FIFO has four or fewer
0 = No data in the receiver FIFO
1 = Data in the receiver FIFO
0 = FIFO is empty or the data in the
1 = Data in the FIFO is > 30 bit times
0 = No FIFO overrun occurred
1 = A FIFO overrun was detected
Programming Model
0x(FF)FFF904
7
6
5
4
3
2
1
RX DATA
r
r
r
r
r
r
r
0
0
0
0
0
0
0
Setting
four slots remaining
slots remaining
FIFO is < 30 bit times old
old
14-13
BIT
0
r
0
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