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Programming Model
10.3.4
Port Pull-up and Pull-down Resistors
The pull-up and pull-down resistors are enabled by setting the pull-up or pull-down enable register's bits to
1. Pull-up and pull-down resistors can be selected individually regardless of whether the I/O port is
selected or not. After reset, Ports A–F, J, K, and M default to the I/O function with internal pull-up or
pull-down enabled. Resistor assignments for individual ports is shown in Table 10-3. Meanwhile, Port G
defaults to the dedicated function, except for the HIZ/P/D/PG3 pin, which defaults to the PG3 function.
10.4
Programming Model
The chapter's remaining sections provide programming information about individual ports.
10.4.1
Port A Registers
The Port A registers are general-purpose 8-bit I/O registers. They consist of the following:
•
Port A direction register (PADIR)
•
Port A data register (PADATA)
•
Port A pull-up enable register (PAPUEN)
Port A functions either as a GPIO (PA[7:0]) or the lower data byte of the data bus (D[7:0]). Port A can be
used as PA[7:0] only when the MC68VZ328 is operating as an 8-bit system by setting the WDTH8 bit in
the system control register (0xFFFFF000). If the MC68VZ328 is operating in either 16-bit or mixed 8- and
16-bit systems, the pins only function as D[7:0].
At reset the WDTH8 bit of the SCR is cleared, resulting in Port A becoming the lower data byte of the data
bus (D[7:0]) with internal pull-up resistors enabled.
In sleep mode, all of the data bus pins (D[15:0]) are individually pulled up with 1 M resistors.
10-6
Table 10-3. Pull-up and Pull-down Resistors by Port
Port
A, B, D, E, G, and J
C
F
K
M
MC68VZ328 User's Manual
Pull-up
Pull-down
All bits
None
None
All bits
Bits 7, 2–0
Bits 6–3
Bits 3–0
Bits 7–4
Bit 5
Bits 4–0
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