Table 6-12 Chip-Select Control Register 1 Description - Motorola MC68VZ328 User Manual

CSCTRL1
BIT 15 14
EUP
EN
TYPE rw
0 0
RESET
Table 6-12. Chip-Select Control Register 1 Description
Name
Reserved Reserved
Bit 15
EUPEN Extra UPSIZ Bit Enable—This bit enables the
Bit 14 BUPS2, CUPS2, and DUPS2 bits to work with
the corresponding UPSIZ configuration bits.
Hence, it provides a larger dynamic range with
smaller granularity for the unprotected memory
sizing.
SR16 16-Bit SRAM Enable—This bit enables the
Bit 13 use of 16-bit SRAM in chip-select group B
memory space. It determines the functions of
the UWE/UB and LWE/LB pins in CSB
read/write cycles.
EWSO Emulation Chip-Select Wait State
Bit 12 Bit 0—This bit is the lowest significant bit of
the EMU wait state register.
DWSO CSD Wait State Bit 0—This bit is the lowest
Bit 11 significant bit of the CSD wait state register.
CWSO CSC Wait State Bit 0—This bit is the lowest
Bit 10 significant bit of the CSC wait state register.
BWSO CSB Wait State Bit 0—This bit is the lowest
Bit 9 significant bit of the CSB wait state register.
AWS0 CSA Wait State Bit 0—This bit is the lowest
Bit 8 significant bit of the CSA wait state register.
Reserved Reserved
Bit 7
DSIZ3 Size Bit 3 for DRAM Chip-Select Address-
Bit 6 ing Space—When set, this bit extends the
DRAM size.
Reserved Reserved
Bit 5
DUPS2 UPSIZ Bit 2 for CSD Register—This is the
Bit 4 most significant bit for UPSIZ[2:0] when the
EUPEN bit is set.
Chip-Select Control Register 1
13 12 11 10
SR EW DW CW
16 S0 S0 S0
rw rw rw rw
0 0 0 0
Description
Chip-Select Logic
9 8 7 6 5
BW AW DSI
S0 S0 Z3
rw rw rw
0 0 0 0 0
0x0000
This bit is reserved and should be set to 0.
0 = EUPEN bit not set.
1 = EUPEN bit set.
0 = UWE and LWE are selected for all CSB
read/write cycles.
1 = UB and LB are selected for all CSB
read/write cycles.
Refer to Table 6-11 on page 6-16 on the emu-
lation chip-select register for the wait state set-
ting.
Refer to Table 6-10 on page 6-14 on the
chip-select register D for the wait state setting.
Refer to Table 6-9 on page 6-12 on the
chip-select register C for the wait state setting.
Refer to Table 6-8 on page 6-10 on the
chip-select register B for the wait state setting.
Refer to Table 6-7 on page 6-8 on the
chip-select register A for the wait state setting.
This bit is reserved and should be set to 0.
If SIZ[2:0] = 000, the CSD0 and CSD1 spaces
are each 8 Mbyte. For 001, each space is
16 Mbyte. Only valid when the DRAM bit of the
CSD register is set.
This bit is reserved and should be set to 0.
For information on calculating unprotected
memory size, see Example 6-1 on page 6-18.
Programming Model
0x(FF)FFF10A
4 3 2 1 BIT 0
DUP CUP BUP
S2 S2 S2
rw rw rw
0 0 0 0 0
Setting
6-17