Motorola MC68VZ328 User Manual page 375

UART clock I/O, see UCLK/DWE/PE3 pin
Timer status register 1, see TSTAT1 register
Timer status register 2, see TSTAT2 register
TIN pin
as a clock input, 12-3
transitions that trigger capture events, 12-3
TMR1 bit
IPR register, 9-18
ISR register, 9-15
TMR2 bit
IPR register, 9-18
ISR register, 9-14
TOUT pin, using to output a pulse on compare, 12-3
TOUT/TIN/PB6 pin
description, 12-3
direction control, 12-3
signals, 2-8
TPRER1 register, 12-8
TPRER2 register, 12-8
TQFP
mechanical drawing, 20-3
package dimensions, 20-3
pin assignments, 20-2
Transmit FIFO has slot available (FIFO status) bit, see
TX AVAIL bit
Transmit polarity bit, see TXPOL bit
Transmitter available for new data bit, see TXAE bit
Transmitter empty enable bit, see TXEE bit
Transmitter enable bit, see TXEN bit
Transmitter half empty enable bit, see TXHE bit
TSTAT1 register, 12-12
TSTAT2 register, 12-12
TX AVAIL bit
UTX1 register, 14-15
UTX2 register, 14-25
Tx data (character) (write-only) field, see TX DATA
field
TX DATA field
UTX1 register, 14-15
UTX2 register, 14-25
TXAE bit
USTCNT1 register, 14-11
USTCNT2 register, 14-21
TXCNT field, 13-10
TXD1/PE5 pin, 2-8
TXD2/PJ5 pin, 2-8
TXEE bit
USTCNT1 register, 14-11
USTCNT2 register, 14-21
TXEN bit
USTCNT1 register, 14-10
USTCNT2 register, 14-20
TxFIFO
buffer operation
UART 1, 14-4
UART 2, 14-5
data for, see DATA field
TxFIFO counter field, see TXCNT field
TxFIFO empty interrupt enable bit, see TEEN bit
TxFIFO empty status bit, see TE bit
TxFIFO full interrupt enable bit, see TFEN bit
TxFIFO full status bit, see TF bit
TxFIFO half interrupt enable bit, see THEN bit
TxFIFO half status bit, see TH bit
TXFIFO LEVEL MARKER field, 14-29
TxFIFO level marker field, see TXFIFO LEVEL
MARKER field
TXHE bit
USTCNT1 register, 14-11
USTCNT2 register, 14-21
TXPOL bit
UMISC1 register, 14-17
UMISC2 register, 14-27
U
UART 1 baud control register, see UBAUD1 register
UART 1 enable bit, see UEN bit
UART 1 interrupt request bit, see UART1 bit
UART 1 miscellaneous register, see UMISC1 register
UART 1 non-integer prescaler register, see NIPR1
register
UART 1 receiver register, see URX1 register
UART 1 status/control register, see USTCNT1 register
UART 1 transmitter register, see UTX1 register
UART 2 baud control register, see UBAUD2 register
UART 2 enable bit, see UEN bit
UART 2 interrupt request bit, see UART2 bit
UART 2 miscellaneous register, see UMISC2 register
UART 2 non-integer prescaler register, see NIPR2
register
UART 2 receiver register, see URX2 register
UART 2 status/control register, see USTCNT2 register
UART 2 transmitter register, see UTX2 register
UART clock, see DWE/UCLK/PE3 pin
UART1 bit, 9-15, 9-18
UART2 bit, 9-14, 9-17
UARTs
features, 14-1
introduction, 14-1
operation
general, 14-2
NRZ mode, 14-2
serial, 14-2
sub-blocks, 14-4
transmitter, 14-4
serial interface signals, 14-3 to 14-4
Index Index-xvii