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LCD screen width register, see LXMAX register
LCD self-refresh on bit, see REF_ON bit
LCD shift clock polarity bit, see LCKPOL bit
LCD source field for PWM counter, see SRC1-0 field
LCD SRAM/ROM DMA cycle 16-bit mode access
timing (1 wait state), 19-13
LCD virtual page width field, see VPx field
LCDCLK SEL field, 4-8
LCDON bit, 8-18
LCKCON register, 8-18
LCKPOL bit, 8-16
LCLK/PC6 pin, 2-7
LCONTRAST/PF0 pin, 2-8
LCWCH register, 8-14
LCWS bit, 6-20
LCXP register, 8-12
LCYP register, 8-13
LD[3:0]/PC[3:0], LD[7:4]/PK[7:4] pins, 2-7
LFLM/PC4 pin, 2-7
LGPMR register, 8-20
Light sleep bit, see LSP bit
Line pulse polarity bit, see LPPOL bit
LLP/PC5 pin, 2-7
LOAD bit, 15-8
Load new setting bit, see LOAD bit
LOOP bit
UMISC1 register, 14-16
UMISC2 register, 14-26
Loop infrared bit, see IRDA LOOP bit
Loopback bit, see LOOP bit
Low-power mode, 8-8
Low-power refresh enable bit, see LPR bit
LPICF register, 8-15
LPOLCF register, 8-16
LPOSR register, 8-19
LPPOL bit, 8-16
LPR bit, 7-15
LPXCD register, 8-17
LRRA register, 8-18
LSP bit, 7-15
LSSA register, 8-10
LVPW register, 8-11
LWE/LB pin, 2-6
LXMAX register, 8-11
LYMAX register, 8-12
M
MA[15:0]/A[16:1] pins, 2-5
MAPBGA
mechanical drawing, 20-5
package dimensions, 20-5
pin assignments, 20-4
Mask emulator interrupt bit, see MEMIQ bit
Mask external INT0 interrupt bit, see MINT0 bit
Mask external INT1 interrupt bit, see MINT1 bit
Mask external INT2 interrupt bit, see MINT2 bit
Mask external INT3 interrupt bit, see MINT3 bit
Mask IRQ1 interrupt bit, see MIRQ1 bit
Mask IRQ2 interrupt bit, see MIRQ2 bit
Mask IRQ3 interrupt bit, see MIRQ3 bit
Mask IRQ5 interrupt bit, see MIRQ5 bit
Mask IRQ6 interrupt bit, see MIRQ6 bit
Mask keyboard interrupt bit, see MKB bit
Mask PWM 1 interrupt bit, see MPWM1 bit
Mask PWM 2 interrupt bit, see MPWM2 bit
Mask RTC interrupt bit, see MRTC bit
Mask SPI 1 interrupt bit, see MSPI1 bit
Mask SPI 2 interrupt bit, see MSPI2 bit
Mask timer 2 interrupt bit, see MTMR2 bit
Mask UART 1 interrupt bit, see MUART1 bit
Mask UART 2 interrupt bit, see MUART2 bit
Mask watchdog timer interrupt bit, see MWDT bit
Master DRAM controller enable bit, see EN bit
Maximum ratings, see electrical characteristics
Maximum width field, see XMx field
MC68VZ328–to–SDRAM connections,
recommendations, 7-5 to 7-6
MEMIQ bit, 9-10
Memory map, see programmer's memory map
Memory, defining areas, 6-1
MINT0 bit, 9-11
MINT1 bit, 9-11
MINT2 bit, 9-11
MINT3 bit, 9-11
MIRQ1 bit, 9-11
MIRQ2 bit, 9-11
MIRQ3 bit, 9-10
MIRQ5 bit, 9-10
MIRQ6 bit, 9-10
MISO signal, 13-3
MISO/PJ1 pin, 2-9
MKB bit, 9-11
MODE bit, 13-6
MOSI signal, 13-3
MOSI/PJ0 pin, 2-9
MPWM1 bit, 9-11
MPWM2 bit, 9-11
MRTC bit, 9-11
MRTI bit, 9-10
MSB for chip-select A field, see AGBA field
MSB for chip-select B field, see BGBA field
MSB for chip-select C field, see CGBA field
MSB for chip-select D field, see DGBA field
MSPI1 bit, 9-10
MSPI2 bit, 9-11
MSW bit, 7-14
MTMR1 bit, 9-11
MTMR2 bit, 9-11
Index
Index-ix
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