Lcd Panel Interface Configuration Register; Table 8-9 Lcd Blink Control Register Description; Table 8-10 Lcd Panel Interface Configuration Register Description - Motorola MC68VZ328 User Manual

LBLKC
BIT 7
BKEN
TYPE rw
0
RESET
Name
BKEN Blink Enable—This bit determines if the cursor will blink or remain
Bit 7 steady.
BDx Blink Divisor 6–0—These bits determine if the cursor will toggle
Bits 6–0 once per a specified number of internal frame pulses plus one. The
half-period may be as long as 2 seconds.
8.3.9

LCD Panel Interface Configuration Register

The LCD panel interface configuration (LPICF) register is used to determine the data bus width of the
LCD panel and to determine if it is a black-and-white or grayscale display. The bit assignments for the
register are shown in the following register display. The settings for the bits in the register are listed in
Table 8-10.
LPICF LCD Panel Interface Configuration Register
BIT 7
TYPE
0
RESET
Table 8-10. LCD Panel Interface Configuration Register Description
Name
Reserved Reserved
Bits 7–4
PBSIZ1–0 Panel Bus Width 1–0—These bits specify
Bits 3–2 the bus width of the LCD panel.
GS1–0 Grayscale Mode Selection 1–0—These
Bits 1–0 bits determine the mode of operation of the
grayscale display device.
LCD Blink Control Register
6 5
BD6 BD5
rw rw
1 1
Table 8-9. LCD Blink Control Register Description
Description
6 5
0 0
Description
LCD Controller
4 3 2
BD4 BD3 BD2
rw rw rw
1 1 1
0x7F
1 = Blink is enabled
0 = Blink is disabled (default)
See description
4 3 2
PBSIZ1–0
rw rw
0 0 0
0x00
Setting
These bits are reserved and should be set to 0.
00 = 1 bit.
01 = 2 bit.
10 = 4 bit.
11 = 8 bit.
00 = Black-and-white mode.
01 = Four-level grayscale mode.
10 = Sixteen-level grayscale mode.
11 = Reserved.
Programming Model
0x(FF)FFFA1F
1 BIT 0
BD1 BD0
rw rw
1 1
Setting
0x(FF)FFFA20
1 BIT 0
GS1–0
rw rw
0 0
8-15