Chip-Select Control Register 2; Table 6-13 Chip-Select Control Register 2 Description - Motorola MC68VZ328 User Manual

Programming Model
Table 6-12. Chip-Select Control Register 1 Description (Continued)
Name
Reserved Reserved
Bit 3
CUPS2 UPSIZ Bit 2 CSC Register—This is the most
Bit 2 significant bit for UPSIZ[2:0] when the EUPEN
bit is set.
Reserved Reserved
Bit 1
BUPS2 UPSIZ Bit 2 CSB Register—This is the most
Bit 0 significant bit for UPSIZ[2:0] when the EUPEN
bit is set.
The unprotected memory size is calculated according to the chip-select addressing space and the UPSIZ
value.
For example, if SIZ[2:0] in CSD = 111 and UPSIZ[2:0] = 011, the unprotected size is calculated as
follows:
(7-3)
4 Mbyte / 2
6.3.6

Chip-Select Control Register 2

This register controls early cycle detection for both static and dynamic types of memory. It improves CPU
access performance by generally removing one CPU wait state or by relaxing the timing requirement for
the memory.
CSCTRL2
BIT 15 14
ECDD ECDS
TYPE rw rw
0 0
RESET
Table 6-13. Chip-Select Control Register 2 Description
Name
ECDD Early Cycle Detection for Dynamic
Bit 15 Memory—This bit advances the timing, allow-
ing the CPU to be used with dynamic memory
access. It reduces wait states by one.
6-18
Description
Example 6-1. Unprotected Memory Size Calculation
Unprotected Size
= 256K
Chip-Select Control Register 2
13 12 11
ECDT EASP
rw rw
0 1 0
Description
MC68VZ328 User's Manual
This bit is reserved and should be set to 0.
For information on calculating unprotected
memory size, see Example 6-1.
This bit is reserved and should be set to 0.
For information on calculating unprotected
memory size, see Example 6-1.
Chip-Select Size
= --------------------------------------- -
7 UPSIZ –
2
10 9 8 7 6
EASDLY[1:0]
rw rw
0 0 0 0 0
0x1000
0 = Disabled.
1 = Enabled.
Setting
0x(FF)FFF10C
5 4 3 2 1 BIT 0
0 0 0 0 0 0
Setting