Table of Contents
Advertisement
Table 6-8. Chip-Select Register B Description (Continued)
Name
WS3–1
Wait State—This field determines the
Bits 6–4
number of wait states added before an
internal DTACK signal is returned for this
chip-select.
Note:
When using the external DTACK
signal, you must configure the
BUSW/DTACK/PG0 pin.
SIZ
Chip-Select Size—This field determines
Bits 3–1
the memory range of the chip-select. For
CSAx and CSBx, the chip-select size is
between 128K and 16 Mbyte. For CSCx
and CSDx, the chip-select size is between
32K and 16 Mbyte.
EN
Chip-Select Enable—This write-only bit
Bit 0
enables each chip-select.
Description
Chip-Select Logic
Setting
000 = 0 + WS0 wait states.
001 = 2 + WS0 wait states.
010 = 4 + WS0 wait states.
011 = 6 + WS0 wait states.
100 = 8 + WS0 wait states.
101 = 10 + WS0 wait states.
110 = 12 + WS0 wait states.
111 = External DTACK.
When using the external DTACK signal, you must
select DTACK function in Port G.
WS0 is the DWS0, CWS0, BWS0, or AWS0 bit in the
CSCTRL1 register.
000 = 128K (32K or 8 Mbyte* for CSCx and CSDx).
001 = 256K (64K or 16 Mbyte* for CSCx and CSDx).
010 = 512K (128K for CSCx and CSDx).
011 = 1 Mbyte (256K for CSCx and CSDx).
100 = 2 Mbyte (512K for CSCx and CSDx).
101 = 4 Mbyte (1 Mbyte for CSCx and CSDx).
110 = 8 Mbyte (2 Mbyte for CSCx and CSDx).
111 = 16 Mbyte (4 Mbyte for CSCx and CSDx).
* Note: Large DRAM size selection requires the DSIZ3
bit in the chip-select control register to be set.
0 = Disabled.
1 = Enabled.
Programming Model
6-11
Advertisement
Table of Contents
