Figure 19-2 Chip-Select Read Cycle Timing Diagram; Table 19-4 Chip-Select Read Cycle Timing Parameters - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
A[31:0]
CSx
UWE/LWE
OE
D[15:0]
DTACK
UDS/LDS
UB/LB
Table 19-4. Chip-Select Read Cycle Timing Parameters
Number
1 Address valid to CSx asserted
(bit ECDS = 0, bit ECDS = 1)
2 UWE/LWE negated before row address valid
3 CSx asserted to OE asserted
4 Data-in valid from CSx asserted
5 External DTACK input setup from CSx asserted
6 CSx pulse width
(bit ECDS = 0, bit ECDS = 1)
7 External DTACK input hold after CSx is negated
8 Data-in hold after CSx is negated
9 OE negated after CSx is negated
10 UB/LB asserted to CSx asserted (16-bit SRAM)
19-4
1
2
4
10
Figure 19-2. Chip-Select Read Cycle Timing Diagram
Characteristic
MC68VZ328 User's Manual
6
3 9
8
5 7
11
(3.0 ± 0.3) V
Minimum
20, 20 - T/2
0
—
—
—
60 + nT,
(60 + T/2) + nT
0
0
0
10
Unit
Maximum
— ns
— ns
0 ns
35 + nT ns
20 + nT ns
— ns
— ns
— ns
10 ns
— ns