Motorola MC68VZ328 User Manual page 167

Table 9-7. Interrupt Pending Register Description (Continued)
Name
IRQ5 Interrupt Request Level 5—This bit, when set, indicates that an
Bit 20 external device is requesting an interrupt on level 5. If the IRQ5 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared.
IRQ6 Interrupt Request Level 6—This bit, when set, indicates that an
Bit 19 external device is requesting an interrupt on level 6. If the IRQ6 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. If IRQ6 is set to be an edge-triggered interrupt,
the interrupt must be cleared by writing a 1 to this bit. Writing a 0 to
this bit has no effect.
IRQ3 Interrupt Request Level 3—This bit, when set, indicates that an
Bit 18 external device is requesting an interrupt on level 3. If the IRQ3 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. If IRQ3 is set to be an edge-triggered interrupt,
the interrupt must be cleared by writing a 1 to this bit. Writing a 0 to
this bit has no effect.
IRQ2 Interrupt Request Level 2—This bit, when set, indicates that an
Bit 17 external device is requesting an interrupt on level 2. If the IRQ2 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. If IRQ2 is set to be an edge-triggered interrupt,
the interrupt must be cleared by writing a 1 to this bit. Writing a 0 to
this bit has no effect.
IRQ1 Interrupt Request Level 1—This bit, when set, indicates that an
Bit 16 external device is requesting an interrupt on level 1. If the IRQ1 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. If IRQ1 is set to be an edge-triggered interrupt,
the interrupt must be cleared by writing a 1 to this bit. Writing a 0 to
this bit has no effect.
Reserved Reserved
Bits 15–14
PWM2 Pulse-Width Modulator 2 Interrupt—This bit indicates an interrupt
Bit 13 event from PWM unit 2 is pending. The interrupt level is configurable
from level 1 to level 6. See Section 9.6.6, "Interrupt Level Register,"
for more details.
UART2 UART 2 Interrupt Request—When this bit is set, it indicates that the
Bit 12 UART 2 module needs service. The interrupt level is configurable
from level 1 to level 6. See Section 9.6.6, "Interrupt Level Register,"
for more details.
INT3 External INT3 Interrupt—This bit, when set, indicates that a level 4
Bit 11 interrupt has occurred. It is usually for a keyboard interface. When it
is programmed as edge-triggered, it can only be cleared by writing a
1 to the port D register. See Section 10.4.5, "Port D Registers," on
page 10-16 for details.
Description
Interrupt Controller
Programming Model
Settings
0 = No level 5 interrupt is
pending.
1 = A level 5 interrupt is
pending.
0 = No level 6 interrupt is
pending.
1 = A level 6 interrupt is
pending.
0 = No level 3 interrupt is
pending.
1 = A level 3 interrupt is
pending.
0 = No level 2 interrupt is
pending.
1 = A level 2 interrupt is
pending.
0 = No level 1 interrupt is
pending.
1 = A level 1 interrupt is
pending.
These bits are reserved and
should be set to 0.
0 = No PWM 2 interrupt.
1 = A PWM 2 interrupt is
pending.
0 = No UART 2 interrupt
request is pending.
1 = UART 2 interrupt request
is pending.
0 = No INT3 interrupt is
pending.
1 = An INT3 interrupt is
pending.
9-17