Port E Dedicated I/O Functions; Table 10-27 Port E Data Register Description; Table 10-28 Port E Dedicated Function Assignments - Motorola MC68VZ328 User Manual

Programming Model
10.4.6.2 Port E Data Register
The settings for the bit positions of the PEDATA register are shown in Table 10-27.
PEDATA
BIT 7
TYPE
RESET
Name Description
Dx Data—These bits reflect the
Bits 7–0 status of the I/O signal in an
8-bit system.
Port E is multiplexed with the serial peripheral interface (SPI), UART, and bus control signals. These pins
can be programmed as GPIO when the SPI, UART, and bus control features are not used. See Chapter 13,
"Serial Peripheral Interface 1 and 2," and Section 2.6, "Bus Control Signals," on page 2-6 for more
detailed information.
These bits control or report the data on the pins while the associated SELx bits are high. While the DIRx
bits are high (output), the Dx bits control the pins. While the DIRx bits are low (input), the Dx bits report
the signal driving the pins. The Dx bits can be written at any time. Bits that are configured as inputs will
accept the data, but the data written to each cannot be accessed until the corresponding pin is configured as
an output. The actual value on the pin is reported when these bits are read, regardless of whether they are
configured as input or output.
10.4.6.3

Port E Dedicated I/O Functions

The eight PEDATA lines are multiplexed with the SPI and UART dedicated I/O signals whose
assignments are shown in Table 10-28.
Table 10-28. Port E Dedicated Function Assignments
Bit
0
1
2
3
4
5
10-22
Port E Data Register
6 5
D7 D6 D5
rw rw rw
1 1 1
*Actual bit value depends on external circuits connected to pin.
Table 10-27. Port E Data Register Description
0 = Drives the output signal low when DIRx is set to 1 or the
1 = Drives the output signal high when DIRx is set to 1 or the
GPIO Function
MC68VZ328 User's Manual
4 3
D4 D3
rw rw
1 1
0xFF*
Setting
external signal is low when DIRx is set to 0
external signal is high when DIRx is set to 0
Dedicated I/O Function
Data bit 0
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
0x(FF)FFF421
2 1 BIT 0
D2 D1 D0
rw rw rw
1 1 1
SPITXD
SPIRXD
SPICLK2
DWE/UCLK
RXD1
TXD1