Port C Direction Register; Port C Data Register; Table 10-12 Port C Direction Register Description; Table 10-13 Port C Data Register Description - Motorola MC68VZ328 User Manual

Motorola mc68vz328 integrated processor user's manual
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10.4.3.1

Port C Direction Register

The Port C direction register controls the direction (input or output) of the line associated with the
PCDATA bit position. When the data bit is assigned to a dedicated I/O function by the PCSEL register, the
DIR bits are ignored. The settings for the bit positions are shown in Table 10-12.
PCDIR
BIT 7
DIR7
TYPE
rw
0
RESET
Name
DIRx
Direction—These bits control the direction of the pins in an 8-bit sys-
Bits 7–0
tem. They reset to 0.
10.4.3.2

Port C Data Register

The settings for the PCDATA bit positions are shown in Table 10-13.
PCDATA
BIT 7
TYPE
RESET
Name
Dx
Data—These bits reflect the
Bits 7–0
status of the I/O signal.
Port C is primarily multiplexed with the LCD controller's signals. These pins can be programmed as GPIO
when the LCD controller is not used. See Section 8.2.1, "Connecting the LCD Controller to an LCD
Panel," on page 8-3 for more detailed information.
These bits control or report the data on the pins while the associated SELx bits are high. While the DIRx
bits are high (output), the Dx bits control the pins. While the DIRx bits are low (input), the Dx bits report
the signal driving the pins. The Dx bits can be written at any time. Bits that are configured as inputs will
10-12
Port C Direction Register
6
5
DIR6
DIR5
rw
rw
0
0
Table 10-12. Port C Direction Register Description
Description
Port C Data Register
6
5
D7
D6
D5
rw
rw
rw
0
0
0
*Actual bit value depends on external circuits connected to pin.
Table 10-13. Port C Data Register Description
Description
0 = Drives the output signal low when DIRx is set to 1 or the
1 = Drives the output signal high when DIRx is set to 1 or the
MC68VZ328 User's Manual
4
3
DIR4
DIR3
rw
rw
0
0
0x00
4
3
D4
D3
rw
rw
0
0
0x00*
Setting
external signal is low when DIRx is set to 0
external signal is high when DIRx is set to 0
0x(FF)FFF410
2
1
BIT 0
DIR2
DIR1
DIR0
rw
rw
rw
0
0
0
Setting
0 = Input
1 = Output
0x(FF)FFF411
2
1
BIT 0
D2
D1
D0
rw
rw
rw
0
0
0

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