Port F Pull-Up/Pull-Down Enable Register; Port F Select Register; Table 10-34 Port F Pull-Up/Pull-Down Enable Register Description; Table 10-35 Port F Select Register Description - Motorola MC68VZ328 User Manual

10.4.7.4

Port F Pull-up/Pull-down Enable Register

The Port F pull-up/pull-down enable register (PFPUEN) controls the pull-up resistors for each line in Port
F. The settings for the PFPUEN bit positions are shown in Table 10-34.
PFPUEN
BIT 7
PU7
TYPE
RESET
Table 10-34. Port F Pull-up/Pull-down Enable Register Description
Name
PU7 Pull-up—This bit enables the pull-up
Bit 7 resistor on the port.
PDx Pull-down—These bits enable the
Bits 6–3 pull-down resistors on the port.
PUx Pull-up—These bits enable the pull-up
Bits 2–0 resistors on the port.
10.4.7.5

Port F Select Register

The Port F select register (PFSEL) determines if a bit position in the data register (PFDATA) is assigned as
a GPIO or to a dedicated I/O function. The settings for the PFSEL bit positions are shown in Table 10-35.
PFSEL
BIT 7
SEL7
TYPE
RESET
Name
SELx Select—These bits select whether the internal chip
Bits 7–0 function or I/O port signals are connected to the pins.
Port F Pull-up/Pull-down Enable Register
6 5
PD6 PD5
rw rw rw
1 1 1
Description
Port F Select Register
6 5
SEL6 SEL5
rw rw rw
1 0 0
Table 10-35. Port F Select Register Description
Description
I/O Ports
4 3 2
PD4 PD3 PU2
rw rw rw
1 1 1
0xFF
Setting
0 = Pull-up resistor is disabled
1 = Pull-up resistor is enabled
0 = Pull-down resistors are disabled
1 = Pull-down resistors are enabled
0 = Pull-up resistors are disabled
1 = Pull-up resistors are enabled
4 3 2
SEL4 SEL3 SEL2
rw rw rw
0 0 1
0x87
0 = The dedicated function pins are connected.
1 = The I/O port function pins are connected.
Programming Model
0x(FF)FFF42A
1 BIT 0
PU1 PU0
rw rw
1 1
0x(FF)FFF42B
1 BIT 0
SEL1 SEL0
rw rw
1 1
Setting
10-27