Pwm 1 Sample Register; Table 15-2 Pwm 1 Sample Register Description - Motorola MC68VZ328 User Manual

Programming Model
15.4.2

PWM 1 Sample Register

This register serves as the input to the FIFO. When successive audio sample values are written to this
register, they are automatically loaded into the FIFO in big-endian format. If 16-bit words are loaded, high
byte is first placed into the 8-bit FIFO, and then low byte. When individual sample bytes are being written,
they must be written to the low byte (SAMPLE1) only. The pulse-width modulator will revert to free
running at the duty-cycle setting that was set last until the FIFO is reloaded or the pulse-width modulator is
disabled. If the value in this register is higher than the PERIOD + 1, the output will never be reset, which
results in a 100-percent duty cycle. The register bit assignments are shown in the following register
display. The register settings are described in Table 15-2.
PWMS1
BIT
14
15
TYPE rw rw
X X
RESET
Name
SAMPLE0 Sample 0—This field represents the high byte of a two-sample word. This byte is pre-
Bits 15–8 sented to the pulse-width modulator before the SAMPLE1 field.
SAMPLE1 Sample 1—This field represents the low byte of a two-sample word. This byte will be
Bits 7–0 presented to the pulse-width modulator after the SAMPLE0 field. When used with single
8-bit samples, data must be written to this byte.
15-6
PWM 1 Sample Register
13 12 11 10
SAMPLE0
rw rw rw rw
X X X X
Table 15-2. PWM 1 Sample Register Description
Description
MC68VZ328 User's Manual
9 8 7 6 5
rw rw rw rw rw
X X X X X
0xXXXX
0x(FF)FFF502
BIT
4 3 2 1
0
SAMPLE1
rw rw rw rw rw
X X X X X
Setting
None
None