Table 6-9 Chip-Select Register C Description - Motorola MC68VZ328 User Manual

Programming Model
CSC
BIT
14
15
RO SOP
TYPE rw rw
0 0
RESET
Name
RO Read-Only—This bit sets the chip-select
Bit 15 to read-only. Otherwise, read and write
accesses are allowed. A write to a
read-only area will generate a bus error if
the BETEN bit of the SCR is set. See
Section 5.2.1, "System Control Register,"
on page 5-2 for more information.
SOP Supervisor-Use-Only Protected Mem-
Bit 14 ory Block—This bit sets the protected
memory block to supervisor-only; other-
wise, both supervisor and user accesses
are allowed. Attempts to access the super-
visor-only area result in a bus error if the
BETEN bit of the SCR is set. See
Section 5.2.1, "System Control Register,"
on page 5-2 for more information.
ROP Read-Only for Protected Memory
Bit 13 Block—This bit sets the protected mem-
ory block to read-only. Otherwise, read
and write accesses are allowed. If you
write to a read-only area, you will get a bus
error.
UPSIZ Unprotected Memory Block Size—This
Bits 12–11 field determines the unprotected memory
range of the chip-select.
Reserved Reserved
Bits 10–9
FLASH Flash Memory Support—When enabled,
Bit 8 this bit provides support for flash memory
by forcing the LWE/UWE signal to go
active after chip-select.
Note: This bit is used for expanded
memory size for CSD when the DRAM bit
in the CSD register is enabled.
BSW Data Bus Width—This bit sets the data
Bit 7 bus width for this chip-select area.
6-12
Chip-Select Register C
13 12 11 10
ROP UPSIZ
rw rw
0 0 0 0
Table 6-9. Chip-Select Register C Description
Description
MC68VZ328 User's Manual
9 8 7 6
FLASH BSW
rw rw rw
0 0 0 0
0x0000
0 = Read/write.
1 = Read-only.
0 = Supervisor/user.
1 = Supervisor-only.
0 = Read/write.
1 = Read-only.
00 = 32K.
01 = 64K.
10 = 128K.
11 = 256K.
These bits are reserved and should be set to 0.
0 = The chip-select and LWE/UWE signals go active at
the same clock edge.
1 = The chip-select signal goes low 1 clock before
LWE/UWE.
0 = 8 bit.
1 = 16 bit.
0x(FF)FFF114
5 4 3 2 1
WS3–1 SIZ
rw rw rw rw rw
0 0 0 0 0
Setting
BIT
0
EN
w
0