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Table 13-3. SPI 1 Control/Status Register Description (Continued)
Name
SSCTL
SS Waveform Select—In master mode, this
Bit 6
bit selects the output wave form for the SS sig-
nal. In slave mode, this bit controls RxFIFO
advancement.
PHA
Phase—This bit controls the clock/data phase
Bit 5
relationship.
POL
Polarity—This bit controls the polarity of the
Bit 4
SCLK signal.
BIT COUNT
Bit Count—This field selects the length of the
Bits 3–0
transfer. A maximum of 16 bits can be trans-
ferred.
In master mode, a 16-bit data word is loaded
from TxFIFO to the shift register, and only the
least significant n bits (n = BIT COUNT) are
shifted out. The next 16-bit word is then loaded
to the shift register.
In slave mode, when the SSCTL bit is 0, this
field controls the number of bits received as a
data word loaded to RxFIFO. When the
SSCTL bit is 1, this field is ignored.
Description
Serial Peripheral Interface 1 and 2
SPI 1 Programming Model
Setting
Master Mode:
0 = SS stays low between SPI 1 bursts
1 = Insert pulse between SPI 1 bursts
Slave Mode:
0 = RxFIFO advanced by Bit Count
1 = RxFIFO advanced by SS rising edge
0 = Phase 0 operation
1 = Phase 1 operation
0 = Active high polarity (0 = idle)
1 = Active low polarity (1 = idle)
0000 = 1-bit transfer
0001 = 2-bit transfer
.
.
.
1110 = 15-bit transfer
1111 = 16-bit transfer
13-7
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