Motorola MC68VZ328 User Manual page 267

Table 14-7. UART 1 Transmitter Register Description (Continued)
Name
FIFO FIFO Half (FIFO Status)—This read-only bit indicates that the
HALF transmitter FIFO is less than half full. This bit generates a
Bit 14 maskable interrupt.
TX Transmit FIFO Available (FIFO Status)—This read-only bit
AVAIL indicates that the transmitter FIFO has at least one slot avail-
Bit 13 able for data. This bit generates a maskable interrupt.
SEND Send Break (Tx Control)—This bit forces the transmitter to
BREAK immediately send continuous zeros, which creates a break
Bit 12 character. See Section 14.3.1.2, "CTS Signal Operation," for a
description of how to generate a break.
NOCTS1 Ignore CTS1 (Tx Control)—When this bit is high, it forces the
Bit 11 CTS1 signal that is presented to the transmitter to always be
asserted, which effectively ignores the external pin.
BUSY Busy (Tx Status)—When this bit is high, it indicates that the
Bit 10 transmitter is busy sending a character. This bit is asserted
while the transmitter state machine is not idle or the FIFO has
data in it.
CTS1 CTS1 Status (CTS1 Bit)—This bit indicates the current status
STAT of the CTS1 signal. A "snapshot" of the pin is taken immedi-
Bit 9 ately before this bit is presented to the data bus. While the
NOCTS1 bit is high, this bit can serve as a general-purpose
input.
CTS1 CTS1 Delta (CTS1 Bit)—When this bit is high, it indicates that
DELTA the CTS1 signal changed state and generates a maskable
Bit 8 interrupt. The current state of the CTS1 signal is available on
the CTS1 STAT bit. An immediate interrupt may be generated
by setting this bit high. The CTS1 interrupt is cleared by writing
0 to this bit.
TX Tx Data (Character) (Write-Only)—This write-only field is the
DATA parallel transmit-data input. In 7-bit mode, bit 7 is ignored, and
Bits 7–0 in 8-bit mode, all of the bits are used. Data is transmitted with
the least significant bit first. A new character is transmitted
when this field is written and has passed through the FIFO.
Universal Asynchronous Receiver/Transmitter 1 and 2
Description
Programming Model
Setting
0 = Transmitter FIFO is more than
half full
1 = Transmitter FIFO is less than
half full
0 = Transmitter does not need data
1 = Transmitter needs data
0 = Normal transmission
1 = Send break (continuous zeros)
0 = Transmit only while the CTS1
signal is asserted
1 = Ignore the CTS1 signal
0 = Transmitter is not sending a
character
1 = Transmitter is sending a
character
0 = CTS1 signal is low
1 = CTS1 signal is high
0 = CTS1 signal did not change
state since it was last cleared
1 = CTS1 signal has changed state
See description
14-15