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Programming Model
6.3.7
Chip-Select Control Register 3
This register controls minor timing trims for static memory access.
CSCTRL3
BIT 15
14
EWE
WPEXT
TYPE
rw
rw
1
0
RESET
Table 6-14. Chip-Select Control Register 3 Description
Name
EWE
End Write Early—When this bit is set, the
Bit 15
RAM write-enable signal negates before the
CS signal is negated.
WPEXT
Write Pulse to CS Negation Margin
Bit 14
Extension—When EWE is set, WPEXT is set
to extend the WE negation to CS negation by
one more clock.
LCWS
Wait State Trim for LCD-SRAM
Bit 13
Access—When this bit is set, one additional
wait state is added to the LCD-SRAM access
cycle. For example, if the wait state is set to
zero, all CPU accesses require 4 cycles to
complete, the chip-select signal to SRAM lasts
2.5 CPU clock cycles, and 2 cycles are used
for LCD access. When LCWS is enabled, the
LCD access is delayed; the access is
increased from 2 to 3 clock cycles.
AST
AS Toggle Enable—Enables AS toggling
Bit 12
between two 8-bit transfers.
DST
DS Toggle Enable—Enables DS toggling
Bit 11
between two 8-bit transfers.
CST
CS Toggle Enable—Enables CS toggling
Bit 10
between two 8-bit transfers.
Reserved
Reserved
–
Bits 9
0
Example 6-2 on page 6-21 demonstrates how to initialize the chip-select with a particular memory
configuration.
6-20
Chip-Select Control Register 3
13
12
11
LCWS
AST
DST
CST
rw
rw
rw
0
1
1
Description
MC68VZ328 User's Manual
10
9
8
7
6
5
rw
1
0
0
0
0
0
0x9C00
0 = Disabled.
1 = Enabled.
0 = Disabled.
1 = Enabled.
0 = No additional wait state added.
1 = One additional wait state added.
0 = Disable AS toggling between two 8-bit
transfers.
1 = Enable AS toggling between two 8-bit
transfers.
0 = Disable DS toggling between two 8-bit
transfers.
1 = Enable DS toggling between two 8-bit
transfers.
0 = Disable CS toggling between two 8-bit
transfers.
1 = Enable CS toggling between two 8-bit
transfers.
These bits are reserved and should be set to
0.
0x(FF)FFF150
4
3
2
1
BIT 0
0
0
0
0
0
Setting
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