Sdram Control Register; Table 7-8 Sdram Control Register Description - Motorola MC68VZ328 User Manual

Programming Model
7.3.3

SDRAM Control Register

This register controls operation when SDRAM is being used. The bit position and values are shown in the
following register display. The details about the register settings are described in Table 7-8.
SDCTRL
BIT
14
15
SDEN CPM
TYPE rw rw
0 0
RESET
Name
SDEN SDRAM Enable—When this bit is set, together with
Bit 15 the DRAM enable bit (bit 9 of the CSD register) being
set and the EDO bit (DRAMC register bit 10) being
cleared, the SDRAM operation is enabled.
CPM Continuous Page Mode—This bit enables the DRAM
Bit 14 to operate in continuous page mode. DRAM will only
be precharged during a page-miss condition.
Reserved Reserved
Bit 13
RE Refresh Enable—This bit enables the refresh cycle for
Bit 12 SDRAM.
IP Initiate All Bank Precharge Command—Setting this
Bit 11 bit triggers the precharge command for all banks of
SDRAM.
MR Initiate Mode Register Set Command—Setting this
Bit 10 bit triggers the load mode register command to
SDRAM.
Reserved Reserved
Bits 9–7
SCOL SDRAM Column Option—This bit selects the SDRAM
Bit 6 column address MD0.
BNKADDH SDRAM High Order Bank Address Line
Bits 5–4 Selection—A 2-bit bank register selection address is
generated by selecting the appropriate CPU address
line. This register bit allows selection of the high order
bit.
7-16
SDRAM Control Register
13 12 11 10
RE IP MR
rw rw rw
0 0 0 0
Table 7-8. SDRAM Control Register Description
Description
MC68VZ328 User's Manual
9 8 7 6 5
SCOL BNKADDH
rw rw
0 0 0 0 1
0x003C
0 = SDRAM disable.
1 = SDRAM enable (see description for
other bits that must be set).
0 = SDRAM not in continuous page mode.
1 = SDRAM in continuous page mode.
This bit is reserved and must be set to 0.
0 = SDRAM Refresh cycle not enabled.
1 = SDRAM refresh cycle enabled.
0 = IP command to SDRAM disabled.
1 = IP command to SDRAM enabled.
0 = MR command to SDRAM disabled.
1 = MR command to SDRAM enabled.
These bits are reserved and should be set
to 0.
0 = PA1 (normally for 16-bit SDRAM).
1 = PA0 (normally for 8-bit SDRAM).
00 = PA20.
01 = PA22.
10 = PA24.
11 = Force this bank address line to 0.
See Table 7-9 on page 7-17 for program-
ming examples.
0x(FF)FFFC04
4 3 2 1 BIT 0
BNKADDL CL RACL
rw rw rw rw rw
1 1 1 0 0
Setting